Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	529739657	11310	0	0
entropy_period_rd_A	529739657	1459	0	0
intr_enable_rd_A	529739657	2555	0	0
prefix_0_rd_A	529739657	1669	0	0
prefix_10_rd_A	529739657	1484	0	0
prefix_1_rd_A	529739657	1515	0	0
prefix_2_rd_A	529739657	1488	0	0
prefix_3_rd_A	529739657	1692	0	0
prefix_4_rd_A	529739657	1665	0	0
prefix_5_rd_A	529739657	1636	0	0
prefix_6_rd_A	529739657	1638	0	0
prefix_7_rd_A	529739657	1755	0	0
prefix_8_rd_A	529739657	1622	0	0
prefix_9_rd_A	529739657	1810	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529739657	11310	0	0
T8	2450	0	0	0
T42	479470	5605	0	0
T43	0	3183	0	0
T53	502113	0	0	0
T58	0	79	0	0
T108	0	4	0	0
T109	0	2	0	0
T110	0	6	0	0
T112	0	86	0	0
T115	0	88	0	0
T119	0	3	0	0
T121	0	2	0	0
T123	375841	0	0	0
T124	666746	0	0	0
T125	1253	0	0	0
T126	44253	0	0	0
T127	702554	0	0	0
T128	92128	0	0	0
T129	544004	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529739657	1459	0	0
T109	22952	116	0	0
T110	21709	54	0	0
T141	5312	6	0	0
T142	124919	156	0	0
T143	1985	3	0	0
T144	26989	131	0	0
T145	144085	271	0	0
T146	4328	15	0	0
T147	6616	39	0	0
T148	2269	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529739657	2555	0	0
T109	22952	157	0	0
T110	21709	73	0	0
T111	1057	7	0	0
T141	5312	53	0	0
T142	124919	251	0	0
T143	1985	5	0	0
T144	26989	152	0	0
T145	144085	473	0	0
T146	4328	15	0	0
T149	1148	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529739657	1669	0	0
T109	22952	63	0	0
T110	21709	35	0	0
T141	5312	8	0	0
T142	124919	283	0	0
T143	1985	6	0	0
T144	26989	108	0	0
T145	144085	451	0	0
T146	4328	9	0	0
T147	6616	13	0	0
T148	2269	6	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529739657	1484	0	0
T109	22952	82	0	0
T110	21709	50	0	0
T142	124919	242	0	0
T143	1985	6	0	0
T144	26989	64	0	0
T145	144085	423	0	0
T146	4328	14	0	0
T147	6616	20	0	0
T148	2269	4	0	0
T150	8197	15	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529739657	1515	0	0
T109	22952	71	0	0
T110	21709	27	0	0
T141	5312	31	0	0
T142	124919	229	0	0
T143	1985	1	0	0
T144	26989	68	0	0
T145	144085	393	0	0
T146	4328	14	0	0
T147	6616	1	0	0
T148	2269	4	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529739657	1488	0	0
T109	22952	90	0	0
T110	21709	30	0	0
T141	5312	15	0	0
T142	124919	238	0	0
T144	26989	85	0	0
T145	144085	454	0	0
T146	4328	11	0	0
T147	6616	12	0	0
T148	2269	5	0	0
T150	8197	10	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529739657	1692	0	0
T109	22952	75	0	0
T110	21709	21	0	0
T141	5312	45	0	0
T142	124919	292	0	0
T143	1985	4	0	0
T144	26989	76	0	0
T145	144085	463	0	0
T146	4328	17	0	0
T147	6616	21	0	0
T148	2269	3	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529739657	1665	0	0
T109	22952	84	0	0
T110	21709	52	0	0
T141	5312	39	0	0
T142	124919	285	0	0
T143	1985	3	0	0
T144	26989	79	0	0
T145	144085	442	0	0
T146	4328	3	0	0
T147	6616	20	0	0
T148	2269	1	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529739657	1636	0	0
T109	22952	78	0	0
T110	21709	45	0	0
T122	9154	8	0	0
T141	5312	34	0	0
T142	124919	261	0	0
T143	1985	1	0	0
T144	26989	66	0	0
T145	144085	423	0	0
T146	4328	19	0	0
T147	6616	22	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529739657	1638	0	0
T109	22952	93	0	0
T110	21709	71	0	0
T141	5312	17	0	0
T142	124919	243	0	0
T143	1985	1	0	0
T144	26989	71	0	0
T145	144085	526	0	0
T146	4328	14	0	0
T147	6616	4	0	0
T148	2269	7	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529739657	1755	0	0
T109	22952	75	0	0
T110	21709	51	0	0
T141	5312	8	0	0
T142	124919	337	0	0
T143	1985	1	0	0
T144	26989	81	0	0
T145	144085	474	0	0
T146	4328	10	0	0
T147	6616	33	0	0
T148	2269	2	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529739657	1622	0	0
T109	22952	92	0	0
T110	21709	45	0	0
T112	9589	2	0	0
T141	5312	14	0	0
T142	124919	196	0	0
T143	1985	4	0	0
T144	26989	85	0	0
T145	144085	465	0	0
T146	4328	12	0	0
T147	6616	50	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529739657	1810	0	0
T109	22952	111	0	0
T110	21709	61	0	0
T141	5312	21	0	0
T142	124919	296	0	0
T143	1985	1	0	0
T144	26989	67	0	0
T145	144085	479	0	0
T146	4328	12	0	0
T147	6616	16	0	0
T148	2269	8	0	0