Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40249431	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

50014994

1

T1

568

T2

440

T3

431

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48598094	1			T1	469		T2	341		T3	343
values[0x0]	20198181	1			T1	56		T2	165		T3	151
values[0x1]	21468150	1			T1	61		T2	157		T3	170

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31231066	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

59033359

1

T1

573

T2

494

T3

492

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	292118	1			T2	1		T3	3		T12	2
valid_sources[0x01]	294623	1			T1	2		T3	1		T4	8
valid_sources[0x02]	293258	1			T1	1		T2	12		T3	1
valid_sources[0x03]	294299	1			T1	3		T12	4		T13	17
valid_sources[0x04]	307259	1			T3	2		T12	4		T13	15
valid_sources[0x05]	291496	1			T2	9		T3	2		T4	3
valid_sources[0x06]	295076	1			T1	5		T2	3		T3	2
valid_sources[0x07]	294319	1			T1	7		T2	1		T3	3
valid_sources[0x08]	293818	1			T1	3		T2	4		T3	3
valid_sources[0x09]	516933	1			T1	2		T3	2		T12	9
valid_sources[0x0a]	294082	1			T1	3		T2	2		T3	5
valid_sources[0x0b]	293809	1			T1	1		T2	4		T3	4
valid_sources[0x0c]	292945	1			T1	2		T3	2		T12	6
valid_sources[0x0d]	295376	1			T2	1		T3	6		T12	3
valid_sources[0x0e]	321312	1			T1	3		T2	1		T3	1
valid_sources[0x0f]	606657	1			T1	6		T2	6		T3	3
valid_sources[0x10]	300951	1			T1	4		T2	5		T3	5
valid_sources[0x11]	345856	1			T1	1		T3	2		T12	1
valid_sources[0x12]	292638	1			T1	4		T2	6		T3	6
valid_sources[0x13]	292044	1			T1	6		T2	5		T3	3
valid_sources[0x14]	292622	1			T1	2		T2	8		T3	1
valid_sources[0x15]	296285	1			T1	3		T3	5		T4	2
valid_sources[0x16]	309898	1			T1	3		T3	1		T12	5
valid_sources[0x17]	293272	1			T2	4		T3	1		T12	3
valid_sources[0x18]	394502	1			T1	1		T2	1		T3	4
valid_sources[0x19]	293599	1			T1	5		T2	2		T3	1
valid_sources[0x1a]	486214	1			T1	1		T3	3		T4	5
valid_sources[0x1b]	299751	1			T1	4		T3	1		T4	14
valid_sources[0x1c]	295663	1			T1	2		T3	10		T12	3
valid_sources[0x1d]	295003	1			T1	1		T2	2		T3	7
valid_sources[0x1e]	467476	1			T1	3		T2	7		T3	1
valid_sources[0x1f]	297261	1			T1	2		T2	6		T3	2
valid_sources[0x20]	294483	1			T2	1		T3	3		T12	5
valid_sources[0x21]	294188	1			T2	6		T3	5		T12	6
valid_sources[0x22]	291846	1			T3	3		T4	8		T12	7
valid_sources[0x23]	294822	1			T1	1		T2	1		T3	2
valid_sources[0x24]	726810	1			T1	2		T2	7		T3	5
valid_sources[0x25]	488730	1			T1	2		T3	4		T12	2
valid_sources[0x26]	290704	1			T1	1		T3	2		T4	3
valid_sources[0x27]	290643	1			T1	5		T2	7		T3	2
valid_sources[0x28]	404574	1			T1	2		T2	3		T3	2
valid_sources[0x29]	294945	1			T1	2		T3	1		T4	1
valid_sources[0x2a]	295808	1			T1	2		T2	6		T3	2
valid_sources[0x2b]	296541	1			T1	2		T2	1		T3	2
valid_sources[0x2c]	291926	1			T1	2		T3	1		T4	5
valid_sources[0x2d]	293487	1			T3	2		T4	1		T12	2
valid_sources[0x2e]	295625	1			T12	5		T13	15		T14	1
valid_sources[0x2f]	297332	1			T1	1		T2	1		T3	4
valid_sources[0x30]	292081	1			T1	2		T3	5		T12	5
valid_sources[0x31]	293970	1			T1	1		T2	1		T3	1
valid_sources[0x32]	292275	1			T1	3		T2	11		T12	3
valid_sources[0x33]	294213	1			T1	1		T2	1		T12	4
valid_sources[0x34]	292663	1			T1	1		T2	4		T3	5
valid_sources[0x35]	296737	1			T1	3		T2	2		T3	4
valid_sources[0x36]	296657	1			T1	5		T3	5		T12	2
valid_sources[0x37]	292411	1			T1	3		T2	6		T3	1
valid_sources[0x38]	291920	1			T1	3		T3	4		T12	3
valid_sources[0x39]	296453	1			T1	3		T3	4		T12	4
valid_sources[0x3a]	291203	1			T1	4		T2	2		T3	2
valid_sources[0x3b]	333729	1			T1	5		T2	2		T3	2
valid_sources[0x3c]	295749	1			T1	1		T2	7		T3	5
valid_sources[0x3d]	290107	1			T1	3		T12	2		T13	12
valid_sources[0x3e]	291837	1			T1	6		T2	6		T3	4
valid_sources[0x3f]	496852	1			T1	1		T2	1		T3	4
valid_sources[0x40]	301726	1			T3	1		T12	1		T13	17
valid_sources[0x41]	360629	1			T3	3		T12	3		T13	11
valid_sources[0x42]	296972	1			T1	1		T3	2		T12	8
valid_sources[0x43]	294998	1			T1	3		T3	2		T12	3
valid_sources[0x44]	364778	1			T1	5		T3	5		T12	4
valid_sources[0x45]	293324	1			T1	1		T3	3		T12	7
valid_sources[0x46]	293277	1			T1	6		T3	7		T4	9
valid_sources[0x47]	476380	1			T1	4		T3	2		T13	5
valid_sources[0x48]	559151	1			T2	8		T3	2		T12	6
valid_sources[0x49]	446508	1			T1	2		T2	12		T3	1
valid_sources[0x4a]	291761	1			T1	6		T3	1		T12	6
valid_sources[0x4b]	427140	1			T1	3		T2	2		T3	1
valid_sources[0x4c]	292268	1			T1	1		T2	2		T3	3
valid_sources[0x4d]	291903	1			T2	1		T3	4		T12	4
valid_sources[0x4e]	294009	1			T1	4		T2	1		T3	1
valid_sources[0x4f]	292123	1			T1	3		T2	6		T3	2
valid_sources[0x50]	750005	1			T3	4		T12	5		T13	23
valid_sources[0x51]	294869	1			T1	2		T2	4		T3	3
valid_sources[0x52]	297143	1			T1	1		T2	5		T4	1
valid_sources[0x53]	293639	1			T2	3		T3	3		T4	2
valid_sources[0x54]	293980	1			T3	5		T12	3		T13	33
valid_sources[0x55]	471408	1			T1	7		T2	6		T3	1
valid_sources[0x56]	297787	1			T1	3		T2	4		T3	6
valid_sources[0x57]	305034	1			T1	6		T2	5		T3	3
valid_sources[0x58]	1359158	1			T1	4		T2	4		T3	1
valid_sources[0x59]	295357	1			T1	3		T2	3		T3	4
valid_sources[0x5a]	293914	1			T1	1		T3	1		T12	3
valid_sources[0x5b]	292919	1			T1	3		T2	3		T12	5
valid_sources[0x5c]	287534	1			T1	3		T12	11		T13	7
valid_sources[0x5d]	296609	1			T1	5		T2	1		T3	3
valid_sources[0x5e]	382003	1			T1	3		T3	1		T4	4
valid_sources[0x5f]	303721	1			T1	1		T2	3		T3	2
valid_sources[0x60]	317951	1			T1	3		T2	2		T3	4
valid_sources[0x61]	292542	1			T1	3		T12	6		T14	1
valid_sources[0x62]	596723	1			T1	2		T2	2		T3	2
valid_sources[0x63]	292542	1			T3	2		T4	2		T12	6
valid_sources[0x64]	290132	1			T1	7		T3	4		T12	6
valid_sources[0x65]	293351	1			T2	5		T3	4		T12	2
valid_sources[0x66]	491342	1			T1	3		T2	1		T3	2
valid_sources[0x67]	289296	1			T1	2		T3	2		T12	5
valid_sources[0x68]	1050727	1			T1	1		T2	2		T3	7
valid_sources[0x69]	1284863	1			T1	4		T2	5		T3	5
valid_sources[0x6a]	321387	1			T1	4		T3	2		T12	10
valid_sources[0x6b]	293332	1			T1	3		T2	7		T3	2
valid_sources[0x6c]	298630	1			T1	1		T2	14		T3	6
valid_sources[0x6d]	291161	1			T1	7		T2	5		T3	2
valid_sources[0x6e]	297366	1			T1	2		T2	7		T3	2
valid_sources[0x6f]	294066	1			T1	2		T2	7		T3	2
valid_sources[0x70]	294722	1			T1	1		T4	5		T12	7
valid_sources[0x71]	291360	1			T1	1		T2	2		T3	4
valid_sources[0x72]	295504	1			T1	1		T2	2		T3	2
valid_sources[0x73]	296303	1			T2	6		T3	2		T4	3
valid_sources[0x74]	1421993	1			T1	1		T2	1		T12	8
valid_sources[0x75]	295198	1			T1	4		T3	3		T12	5
valid_sources[0x76]	290062	1			T1	1		T2	12		T3	4
valid_sources[0x77]	489351	1			T12	4		T13	2		T14	1
valid_sources[0x78]	292283	1			T1	1		T3	2		T12	3
valid_sources[0x79]	413707	1			T1	3		T2	5		T3	3
valid_sources[0x7a]	298419	1			T1	1		T3	2		T12	2
valid_sources[0x7b]	293946	1			T1	2		T3	3		T4	1
valid_sources[0x7c]	1432817	1			T1	6		T2	6		T3	1
valid_sources[0x7d]	293600	1			T1	3		T3	5		T12	2
valid_sources[0x7e]	291995	1			T1	1		T2	3		T3	2
valid_sources[0x7f]	423143	1			T1	2		T2	1		T3	3
valid_sources[0x80]	295912	1			T1	1		T2	2		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23742778

1

T1

462

T2

217

T3

219

values[0x0]

all_enables

biggest_size

13779616

1

T1

52

T2

122

T3

114

values[0x1]

all_enables

biggest_size

12492600

1

T1

54

T2

101

T3

98