Unified Coverage Report :: Group :: cip_base_pkg::resets_cg

Group : cip_base_pkg::resets_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
cip_base_pkg.dut_and_edn_rsts	100.00	1	100	1	64	64

---

Group Instance : cip_base_pkg.dut_and_edn_rsts

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance cip_base_pkg.dut_and_edn_rsts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance cip_base_pkg.dut_and_edn_rsts

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
resets_trans	4	0	4	100.00	100	1	1	0

Summary for Variable resets_trans

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for resets_trans

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
rst1_start_last_end_first	270	1			T4	1		T10	38		T11	35
rst1_start_first_end_last	318	1			T6	22		T10	65		T11	24
rst1_start_last_end_last	634	1			T6	198		T10	73		T11	21
rst1_start_first_end_first	387	1			T5	1		T46	1		T10	44