Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

40321559

1

T1

18

T2

223

T3

233

full_word

50019581

1

T1

568

T2

440

T3

431

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	90340870	1			T1	586		T2	663		T3	664
auto[TlIntgErrCmd]	89	1			T129	4		T130	4		T131	6
auto[TlIntgErrData]	79	1			T129	2		T130	9		T131	6
auto[TlIntgErrBoth]	102	1			T129	4		T130	7		T131	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48615173

1

T1

469

T2

341

T3

343

auto[1]

41725967

1

T1

117

T2

322

T3

321

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	24870923	1			T1	7		T2	124		T3	124
auto[TlIntgErrNone]	partial	auto[1]	15450382	1			T1	11		T2	99		T3	109
auto[TlIntgErrNone]	full_word	auto[0]	23744130	1			T1	462		T2	217		T3	219
auto[TlIntgErrNone]	full_word	auto[1]	26275435	1			T1	106		T2	223		T3	212
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T129	2		T130	3		T131	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T129	1		T130	1		T131	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T129	1		T172	1		T173	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T131	1		T173	1		-	-
auto[TlIntgErrData]	partial	auto[0]	38	1			T129	1		T130	7		T131	5
auto[TlIntgErrData]	partial	auto[1]	37	1			T129	1		T130	2		T131	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T174	1		T175	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T176	1		T177	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T129	2		T130	5		T131	2
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T129	2		T130	1		T131	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T130	1		T131	1		T176	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T167	1		T178	1		T173	2