Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	526306478	13414	0	0
entropy_period_rd_A	526306478	1679	0	0
intr_enable_rd_A	526306478	2304	0	0
prefix_0_rd_A	526306478	1516	0	0
prefix_10_rd_A	526306478	1426	0	0
prefix_1_rd_A	526306478	1471	0	0
prefix_2_rd_A	526306478	1379	0	0
prefix_3_rd_A	526306478	1481	0	0
prefix_4_rd_A	526306478	1438	0	0
prefix_5_rd_A	526306478	1400	0	0
prefix_6_rd_A	526306478	1291	0	0
prefix_7_rd_A	526306478	1443	0	0
prefix_8_rd_A	526306478	1453	0	0
prefix_9_rd_A	526306478	1431	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526306478	13414	0	0
T5	4169	0	0	0
T18	103073	527	0	0
T21	372520	0	0	0
T32	141889	0	0	0
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T50	0	5159	0	0
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T130	0	1	0	0
T135	0	1310	0	0
T136	0	1030	0	0
T137	0	231	0	0
T138	0	1	0	0
T139	0	186	0	0
T140	0	3	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526306478	1679	0	0
T5	4169	0	0	0
T18	103073	26	0	0
T21	372520	0	0	0
T32	141889	0	0	0
T44	0	57	0	0
T64	147424	0	0	0
T65	89499	0	0	0
T77	2952	0	0	0
T92	175152	0	0	0
T93	240159	0	0	0
T94	58092	0	0	0
T104	0	15	0	0
T105	0	55	0	0
T107	0	109	0	0
T109	0	69	0	0
T130	0	112	0	0
T152	0	199	0	0
T153	0	54	0	0
T154	0	263	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526306478	2304	0	0
T5	4169	0	0	0
T18	103073	20	0	0
T21	372520	0	0	0
T32	141889	0	0	0
T44	0	51	0	0
T64	147424	0	0	0
T65	89499	0	0	0
T77	2952	0	0	0
T92	175152	0	0	0
T93	240159	0	0	0
T94	58092	0	0	0
T104	0	19	0	0
T105	0	35	0	0
T107	0	85	0	0
T130	0	145	0	0
T132	0	14	0	0
T134	0	11	0	0
T152	0	188	0	0
T155	0	15	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526306478	1516	0	0
T5	4169	0	0	0
T18	103073	7	0	0
T21	372520	0	0	0
T32	141889	0	0	0
T44	0	54	0	0
T64	147424	0	0	0
T65	89499	0	0	0
T77	2952	0	0	0
T92	175152	0	0	0
T93	240159	0	0	0
T94	58092	0	0	0
T104	0	12	0	0
T105	0	25	0	0
T107	0	73	0	0
T109	0	81	0	0
T130	0	79	0	0
T152	0	256	0	0
T153	0	16	0	0
T154	0	233	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526306478	1426	0	0
T5	4169	0	0	0
T18	103073	15	0	0
T21	372520	0	0	0
T32	141889	0	0	0
T44	0	58	0	0
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T65	89499	0	0	0
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T92	175152	0	0	0
T93	240159	0	0	0
T94	58092	0	0	0
T104	0	11	0	0
T105	0	20	0	0
T107	0	52	0	0
T109	0	56	0	0
T130	0	60	0	0
T152	0	247	0	0
T153	0	28	0	0
T154	0	171	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526306478	1471	0	0
T5	4169	0	0	0
T18	103073	28	0	0
T21	372520	0	0	0
T32	141889	0	0	0
T44	0	40	0	0
T64	147424	0	0	0
T65	89499	0	0	0
T77	2952	0	0	0
T92	175152	0	0	0
T93	240159	0	0	0
T94	58092	0	0	0
T104	0	15	0	0
T105	0	25	0	0
T107	0	57	0	0
T109	0	43	0	0
T130	0	98	0	0
T152	0	207	0	0
T153	0	24	0	0
T154	0	191	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526306478	1379	0	0
T5	4169	0	0	0
T18	103073	22	0	0
T21	372520	0	0	0
T32	141889	0	0	0
T44	0	48	0	0
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T65	89499	0	0	0
T77	2952	0	0	0
T92	175152	0	0	0
T93	240159	0	0	0
T94	58092	0	0	0
T104	0	13	0	0
T105	0	25	0	0
T107	0	56	0	0
T109	0	58	0	0
T130	0	59	0	0
T152	0	212	0	0
T153	0	60	0	0
T154	0	298	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526306478	1481	0	0
T5	4169	0	0	0
T18	103073	21	0	0
T21	372520	0	0	0
T32	141889	0	0	0
T44	0	56	0	0
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T65	89499	0	0	0
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T92	175152	0	0	0
T93	240159	0	0	0
T94	58092	0	0	0
T104	0	21	0	0
T105	0	19	0	0
T107	0	50	0	0
T109	0	79	0	0
T130	0	83	0	0
T152	0	193	0	0
T153	0	17	0	0
T154	0	251	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526306478	1438	0	0
T5	4169	0	0	0
T18	103073	23	0	0
T21	372520	0	0	0
T32	141889	0	0	0
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T93	240159	0	0	0
T94	58092	0	0	0
T104	0	5	0	0
T105	0	14	0	0
T107	0	73	0	0
T109	0	64	0	0
T130	0	72	0	0
T152	0	181	0	0
T153	0	26	0	0
T154	0	249	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526306478	1400	0	0
T5	4169	0	0	0
T18	103073	12	0	0
T21	372520	0	0	0
T32	141889	0	0	0
T44	0	45	0	0
T64	147424	0	0	0
T65	89499	0	0	0
T77	2952	0	0	0
T92	175152	0	0	0
T93	240159	0	0	0
T94	58092	0	0	0
T104	0	5	0	0
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T130	0	84	0	0
T152	0	212	0	0
T153	0	37	0	0
T154	0	238	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
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T5	4169	0	0	0
T18	103073	12	0	0
T21	372520	0	0	0
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prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
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T5	4169	0	0	0
T18	103073	18	0	0
T21	372520	0	0	0
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T130	0	98	0	0
T152	0	246	0	0
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prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
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T5	4169	0	0	0
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prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
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T5	4169	0	0	0
T18	103073	12	0	0
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