LC_CTRL Simulation Results

Wednesday May 17 2023 07:05:42 UTC

GitHub Revision: `3df77bec1`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 2320738200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.030s	664.427us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.320s	23.222us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	17.691us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.060s	52.319us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.380s	20.844us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.870s	25.279us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	17.691us	20	20	100.00
		lc_ctrl_csr_aliasing	1.380s	20.844us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	14.320s	96.407us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	17.510s	316.181us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	10.858us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.210s	194.536us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	1.017m	242.310us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.190s	876.298us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	1.017m	242.310us	50	50	100.00
		lc_ctrl_prog_failure	4.210s	194.536us	50	50	100.00
		lc_ctrl_errors	24.190s	876.298us	50	50	100.00
		lc_ctrl_security_escalation	14.250s	2.516ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.758m	4.929ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.110s	941.863us	20	20	100.00
		lc_ctrl_jtag_errors	1.839m	4.480ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	18.740s	792.150us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	46.280s	1.428ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.110s	941.863us	20	20	100.00
		lc_ctrl_jtag_errors	1.839m	4.480ms	20	20	100.00
		lc_ctrl_jtag_access	32.330s	1.523ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	43.430s	1.788ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.160s	277.612us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.700s	99.886us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	21.370s	2.659ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	28.970s	1.414ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.430s	137.280us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.230s	212.918us	10	10	100.00
		lc_ctrl_jtag_alert_test	4.000s	168.691us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	40.990s	1.985ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.300s	21.219us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.541m	38.203ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.370s	30.142us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	6.010s	158.999us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	6.010s	158.999us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.320s	23.222us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	17.691us	20	20	100.00
		lc_ctrl_csr_aliasing	1.380s	20.844us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	49.285us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.320s	23.222us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	17.691us	20	20	100.00
		lc_ctrl_csr_aliasing	1.380s	20.844us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	49.285us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	1.049m	972.945us	5	5	100.00
		lc_ctrl_tl_intg_err	4.880s	302.911us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.880s	302.911us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	17.510s	316.181us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	1.017m	242.310us	50	50	100.00
		lc_ctrl_sec_cm	1.049m	972.945us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	1.017m	242.310us	50	50	100.00
		lc_ctrl_sec_cm	1.049m	972.945us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	1.017m	242.310us	50	50	100.00
		lc_ctrl_sec_cm	1.049m	972.945us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	1.017m	242.310us	50	50	100.00
		lc_ctrl_sec_cm	1.049m	972.945us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	1.017m	242.310us	50	50	100.00
		lc_ctrl_sec_cm	1.049m	972.945us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	1.017m	242.310us	50	50	100.00
		lc_ctrl_sec_cm	1.049m	972.945us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	1.017m	242.310us	50	50	100.00
		lc_ctrl_sec_cm	1.049m	972.945us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	1.017m	242.310us	50	50	100.00
		lc_ctrl_sec_cm	1.049m	972.945us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.250s	2.516ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	14.320s	96.407us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	46.280s	1.428ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	20.280s	692.515us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	20.280s	692.515us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.100s	646.612us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	22.220s	739.596us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	22.220s	739.596us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	23.826m	92.026ms	8	50	16.00
V3		TOTAL			8	50	16.00
		TOTAL			988	1030	95.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.25	97.18	95.08	91.98	100.00	95.88	98.48	95.18

Failure Buckets

Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 27 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 27 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.455117633
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:91fb21b3-248c-408b-a226-642c7b2b7c36
```
  - 3.lc_ctrl_stress_all_with_rand_reset.1898145752
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:feca5e85-6641-47fe-9bb8-c5e1d1721110
```
  - ... and 25 more failures.
Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 5 failures.
  - 11.lc_ctrl_stress_all_with_rand_reset.2385768375
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:f68e781c-7a10-4eb4-8522-8dce7aadef24
```
  - 26.lc_ctrl_stress_all_with_rand_reset.944334670
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:542e164c-9293-4946-a80e-e6aff586c659
```
  - ... and 3 more failures.

UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 3 failures:

Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

7.lc_ctrl_stress_all_with_rand_reset.403057296
Line 5090, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 9518880556 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x14bb9c00
  UVM_INFO @ 9518880556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.lc_ctrl_stress_all_with_rand_reset.1156415850
Line 24813, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 141157402081 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xaf81d200
  UVM_INFO @ 141157402081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * called from ../src/lowrisc_dv_lc_ctrl_env_*/seq_lib/lc_ctrl_errors_vseq.sv: * has 2 failures:

Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

5.lc_ctrl_stress_all_with_rand_reset.1116580297
Line 694, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 569464020 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 290
  UVM_INFO @ 569464020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.lc_ctrl_stress_all_with_rand_reset.341994398
Line 866, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 867602366 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 290
  UVM_INFO @ 867602366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 2 failures:

Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

24.lc_ctrl_stress_all_with_rand_reset.1001883596
Line 19932, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 36835447036 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @ 36835447036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.lc_ctrl_stress_all_with_rand_reset.1679031867
Line 9585, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 40345121853 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @ 40345121853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:519) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 12.lc_ctrl_stress_all_with_rand_reset.3536580658
    Line 31409, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25633398622 ps: (cip_base_vseq.sv:519) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 25633398622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:519) [lc_ctrl_regwen_during_op_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 27.lc_ctrl_stress_all_with_rand_reset.1294555606
    Line 357, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1055821701 ps: (cip_base_vseq.sv:519) [uvm_test_top.env.virtual_sequencer.lc_ctrl_regwen_during_op_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
  UVM_INFO @ 1055821701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.initialized reset value: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 47.lc_ctrl_stress_all_with_rand_reset.3960466535
    Line 2399, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2408565846 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.initialized reset value: 0x0
  UVM_INFO @ 2408565846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```