Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	426445	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

591840

1

T46

375

T69

149

T70

375

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	749750	1			T46	26		T69	45		T70	26
values[0x0]	134575	1			T46	165		T69	61		T70	165
values[0x1]	133960	1			T46	184		T69	61		T70	184

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	338250	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

680035

1

T46

375

T69

153

T70

375

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1760	1			T73	3		T92	10		T95	3
valid_sources[0x01]	2705	1			T46	1		T70	1		T73	4
valid_sources[0x02]	1625	1			T46	1		T70	1		T73	4
valid_sources[0x03]	3420	1			T73	1		T92	7		T95	1
valid_sources[0x04]	3990	1			T92	8		T136	8		T142	8
valid_sources[0x05]	2060	1			T78	5		T79	5		T80	5
valid_sources[0x06]	4210	1			T73	2		T92	17		T95	2
valid_sources[0x07]	4000	1			T46	4		T70	4		T92	8
valid_sources[0x08]	4185	1			T81	1		T127	1		T129	1
valid_sources[0x09]	3175	1			T46	5		T70	5		T73	2
valid_sources[0x0a]	2890	1			T46	4		T70	4		T73	3
valid_sources[0x0b]	4030	1			T73	5		T95	5		T96	5
valid_sources[0x0c]	3665	1			T73	2		T95	2		T96	2
valid_sources[0x0d]	7535	1			T92	1		T98	1		T78	10
valid_sources[0x0e]	2370	1			T92	12		T136	12		T142	12
valid_sources[0x0f]	6080	1			T73	1		T92	2		T95	1
valid_sources[0x10]	4600	1			T73	3		T95	3		T96	3
valid_sources[0x11]	2410	1			T73	1		T92	4		T95	1
valid_sources[0x12]	4660	1			T69	2		T73	1		T71	2
valid_sources[0x13]	2840	1			T46	3		T70	3		T73	3
valid_sources[0x14]	4945	1			T46	1		T70	1		T73	3
valid_sources[0x15]	3710	1			T69	1		T73	1		T71	1
valid_sources[0x16]	1800	1			T46	3		T70	3		T73	1
valid_sources[0x17]	7940	1			T81	3		T78	8		T79	8
valid_sources[0x18]	2355	1			T46	4		T70	4		T93	4
valid_sources[0x19]	4910	1			T46	2		T70	2		T73	3
valid_sources[0x1a]	1580	1			T73	2		T95	2		T96	2
valid_sources[0x1b]	3350	1			T73	2		T95	2		T96	2
valid_sources[0x1c]	3105	1			T46	4		T70	4		T73	2
valid_sources[0x1d]	2050	1			T81	2		T78	3		T79	3
valid_sources[0x1e]	2730	1			T46	1		T69	2		T70	1
valid_sources[0x1f]	2400	1			T46	1		T70	1		T93	1
valid_sources[0x20]	3785	1			T46	3		T70	3		T73	4
valid_sources[0x21]	4350	1			T92	13		T81	1		T78	7
valid_sources[0x22]	3500	1			T73	3		T92	2		T95	3
valid_sources[0x23]	2845	1			T73	1		T95	1		T96	1
valid_sources[0x24]	2145	1			T46	3		T70	3		T93	3
valid_sources[0x25]	7860	1			T73	10		T95	10		T96	10
valid_sources[0x26]	2035	1			T73	2		T92	4		T95	2
valid_sources[0x27]	5015	1			T46	1		T69	9		T70	1
valid_sources[0x28]	3290	1			T3	16		T9	4		T11	4
valid_sources[0x29]	5860	1			T46	1		T70	1		T73	5
valid_sources[0x2a]	2810	1			T46	2		T69	5		T70	2
valid_sources[0x2b]	6690	1			T3	3		T9	6		T11	40
valid_sources[0x2c]	4360	1			T73	1		T92	5		T95	1
valid_sources[0x2d]	6220	1			T46	1		T70	1		T92	6
valid_sources[0x2e]	2660	1			T92	4		T136	4		T121	2
valid_sources[0x2f]	6545	1			T92	5		T136	5		T142	5
valid_sources[0x30]	2960	1			T46	3		T70	3		T93	3
valid_sources[0x31]	2415	1			T121	1		T124	1		T126	1
valid_sources[0x32]	4540	1			T92	17		T81	3		T136	17
valid_sources[0x33]	1590	1			T46	6		T69	3		T70	6
valid_sources[0x34]	3355	1			T92	2		T78	8		T79	8
valid_sources[0x35]	2080	1			T73	2		T95	2		T81	1
valid_sources[0x36]	2360	1			T46	2		T70	2		T73	5
valid_sources[0x37]	4015	1			T46	2		T70	2		T73	4
valid_sources[0x38]	3950	1			T69	3		T71	3		T92	9
valid_sources[0x39]	1650	1			T73	2		T95	2		T96	2
valid_sources[0x3a]	3775	1			T121	1		T124	1		T126	1
valid_sources[0x3b]	8650	1			T46	4		T70	4		T73	3
valid_sources[0x3c]	4915	1			T73	4		T95	4		T96	4
valid_sources[0x3d]	2405	1			T69	4		T73	4		T71	4
valid_sources[0x3e]	3760	1			T92	5		T78	1		T79	1
valid_sources[0x3f]	3080	1			T73	1		T95	1		T96	1
valid_sources[0x40]	1790	1			T73	1		T92	5		T95	1
valid_sources[0x41]	3930	1			T73	1		T95	1		T96	1
valid_sources[0x42]	3970	1			T92	13		T136	13		T121	1
valid_sources[0x43]	5665	1			T73	1		T92	3		T95	1
valid_sources[0x44]	3730	1			T46	10		T70	10		T93	10
valid_sources[0x45]	6075	1			T69	3		T73	2		T71	3
valid_sources[0x46]	4410	1			T73	1		T92	8		T95	1
valid_sources[0x47]	3295	1			T73	2		T92	8		T95	2
valid_sources[0x48]	2000	1			T69	5		T73	1		T71	5
valid_sources[0x49]	3450	1			T73	2		T95	2		T96	2
valid_sources[0x4a]	1535	1			T46	8		T69	4		T70	8
valid_sources[0x4b]	6010	1			T46	9		T69	7		T70	9
valid_sources[0x4c]	4805	1			T69	13		T73	1		T71	13
valid_sources[0x4d]	2030	1			T92	2		T81	7		T98	1
valid_sources[0x4e]	3310	1			T46	2		T70	2		T93	2
valid_sources[0x4f]	4265	1			T46	3		T70	3		T73	6
valid_sources[0x50]	2415	1			T46	2		T70	2		T93	2
valid_sources[0x51]	2525	1			T46	1		T70	1		T73	4
valid_sources[0x52]	2800	1			T73	1		T95	1		T96	1
valid_sources[0x53]	3180	1			T92	8		T136	8		T121	2
valid_sources[0x54]	3920	1			T73	3		T95	3		T96	3
valid_sources[0x55]	4090	1			T73	2		T92	8		T95	2
valid_sources[0x56]	3050	1			T73	5		T92	5		T95	5
valid_sources[0x57]	4030	1			T73	4		T92	2		T95	4
valid_sources[0x58]	3880	1			T73	1		T92	13		T95	1
valid_sources[0x59]	4975	1			T73	8		T92	3		T95	8
valid_sources[0x5a]	5465	1			T46	11		T70	11		T73	1
valid_sources[0x5b]	3530	1			T46	7		T70	7		T73	5
valid_sources[0x5c]	1950	1			T73	3		T95	3		T96	3
valid_sources[0x5d]	3480	1			T69	7		T71	7		T72	7
valid_sources[0x5e]	4030	1			T46	3		T70	3		T73	1
valid_sources[0x5f]	3260	1			T73	1		T92	2		T95	1
valid_sources[0x60]	4665	1			T73	2		T92	8		T95	2
valid_sources[0x61]	2810	1			T73	1		T92	7		T95	1
valid_sources[0x62]	2130	1			T73	2		T92	2		T95	2
valid_sources[0x63]	2735	1			T46	8		T70	8		T73	3
valid_sources[0x64]	3035	1			T46	2		T70	2		T92	14
valid_sources[0x65]	1740	1			T73	3		T92	4		T95	3
valid_sources[0x66]	2970	1			T78	1		T79	1		T80	1
valid_sources[0x67]	6625	1			T73	2		T92	21		T95	2
valid_sources[0x68]	2080	1			T78	3		T79	3		T80	3
valid_sources[0x69]	5315	1			T92	15		T78	4		T79	4
valid_sources[0x6a]	2640	1			T69	2		T73	2		T71	2
valid_sources[0x6b]	3285	1			T46	2		T70	2		T73	2
valid_sources[0x6c]	2640	1			T46	8		T70	8		T73	2
valid_sources[0x6d]	1890	1			T46	1		T70	1		T73	2
valid_sources[0x6e]	5140	1			T73	4		T92	3		T95	4
valid_sources[0x6f]	4010	1			T46	2		T70	2		T93	2
valid_sources[0x70]	3800	1			T46	2		T70	2		T93	2
valid_sources[0x71]	6890	1			T46	2		T70	2		T73	4
valid_sources[0x72]	6645	1			T69	2		T73	4		T71	2
valid_sources[0x73]	2740	1			T46	8		T70	8		T73	2
valid_sources[0x74]	3800	1			T69	3		T73	7		T71	3
valid_sources[0x75]	3835	1			T46	5		T70	5		T73	1
valid_sources[0x76]	3915	1			T46	2		T70	2		T73	2
valid_sources[0x77]	4495	1			T78	9		T79	9		T80	9
valid_sources[0x78]	2860	1			T69	7		T73	4		T71	7
valid_sources[0x79]	2205	1			T73	2		T92	7		T95	2
valid_sources[0x7a]	5930	1			T46	1		T70	1		T93	1
valid_sources[0x7b]	3140	1			T69	2		T73	1		T71	2
valid_sources[0x7c]	3995	1			T92	5		T136	5		T121	5
valid_sources[0x7d]	3650	1			T46	4		T70	4		T93	4
valid_sources[0x7e]	3395	1			T73	4		T92	11		T95	4
valid_sources[0x7f]	6760	1			T46	8		T70	8		T93	8
valid_sources[0x80]	4560	1			T73	1		T92	2		T95	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

362755

1

T46

26

T69

32

T70

26

values[0x0]

all_enables

biggest_size

115550

1

T46

165

T69

60

T70

165

values[0x1]

all_enables

biggest_size

113535

1

T46

184

T69

57

T70

184