Unified Coverage Report :: Group :: dv_base_reg_pkg::mubi_cov#(8,32'sh00000096,32'sh00000069)::mubi_cg

Group : dv_base_reg_pkg::mubi_cov#(8,32'sh00000096,32'sh00000069)::mubi_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
20.00	20.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex	20.00	1	100	1	64	64

---

Group Instance : mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
20.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	8	2	20.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	8	2	20.00	100	1	1	0

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	8	2	20.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
others[1]	0	1	1
others[2]	0	1	1
others[3]	0	1	1
others[4]	0	1	1
others[5]	0	1	1
others[6]	0	1	1
others[7]	0	1	1
false	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

others[0]

4880

1

T6

38

T7

38

T8

38

true

46200

1

T1

18

T2

18

T3

18