Unified Coverage Report :: Module :: dmi_cdc

Module : dmi_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.36			96.36

Source File(s) :
/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag.i_dmi_cdc	96.36			96.36

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.36			96.36

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.65			96.65

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.56			95.56				u_dmi_jtag

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
i_cdc_req	99.32			99.32
i_cdc_resp	96.99			96.99
u_combined_rstn_sync	86.96			86.96
u_rst_mux	75.00			75.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : dmi_cdc

	Total	Covered	Percent
Totals	25	21	84.00
Total Bits	330	318	96.36
Total Bits 0->1	165	159	96.36
Total Bits 1->0	165	159	96.36

Ports	25	21	84.00
Port Bits	330	318	96.36
Port Bits 0->1	165	159	96.36
Port Bits 1->0	165	159	96.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
testmode_i	No	No		No		INPUT
test_rst_ni	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	INPUT
tck_i	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
trst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_dmi_req_i.data[31:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
jtag_dmi_req_i.op[1:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
jtag_dmi_req_i.addr[6:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
jtag_dmi_ready_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
jtag_dmi_valid_i	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
jtag_dmi_cdc_clear_i	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
jtag_dmi_resp_o.resp[1:0]	No	No		No		OUTPUT
jtag_dmi_resp_o.data[31:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
jtag_dmi_valid_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
jtag_dmi_ready_i	Unreachable	Unreachable		Unreachable		INPUT
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_dmi_rst_no	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
core_dmi_req_o.data[31:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
core_dmi_req_o.op[1:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
core_dmi_req_o.addr[5:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
core_dmi_req_o.addr[6]	No	No		No		OUTPUT
core_dmi_valid_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
core_dmi_ready_i	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
core_dmi_resp_i.resp[1:0]	No	No		No		INPUT
core_dmi_resp_i.data[31:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
core_dmi_ready_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
core_dmi_valid_i	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT