Module Definition
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Module Instance : tb.dut.u_prim_lc_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.75 100.00 83.10 98.16 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.32 97.73 93.18 100.00 97.33 93.33 u_lc_ctrl_fsm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.32 97.73 93.18 100.00 97.33 93.33 u_lc_ctrl_fsm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.32 97.73 93.18 100.00 97.33 93.33 u_lc_ctrl_fsm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.32 97.73 93.18 100.00 97.33 93.33 u_lc_ctrl_fsm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=4,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack

Line No.TotalCoveredPercent
TOTAL55100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 4 4


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 2 2


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=4,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid

Line No.TotalCoveredPercent
TOTAL55100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 4 4


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=8,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid

Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 8 8


Assert Coverage for Module : prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 3985 3985 0 0
OutputsKnown_A 269756990 254839320 0 0
gen_flops.OutputDelay_A 107809275 101632125 0 4704
gen_no_flops.OutputDelay_A 161947715 152969649 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3985 3985 0 0
T1 5 5 0 0
T2 5 5 0 0
T3 5 5 0 0
T4 5 5 0 0
T5 5 5 0 0
T6 5 5 0 0
T11 5 5 0 0
T12 5 5 0 0
T13 5 5 0 0
T14 5 5 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 269756990 254839320 0 0
T1 331615 331345 0 0
T2 10520 10045 0 0
T3 188650 152495 0 0
T4 106275 81655 0 0
T5 136598 117940 0 0
T6 150155 145910 0 0
T11 196530 176620 0 0
T12 35295 31735 0 0
T13 198990 164985 0 0
T14 168905 138795 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 107809275 101632125 0 4704
T1 132646 132532 0 6
T2 4208 4012 0 6
T3 75460 60422 0 6
T4 42510 32254 0 6
T5 54369 47128 0 3
T6 60062 58298 0 6
T11 78612 70330 0 6
T12 14118 12634 0 6
T13 79596 65454 0 6
T14 67562 55032 0 6
T23 0 0 0 3

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161947715 152969649 0 0
T1 198969 198807 0 0
T2 6312 6027 0 0
T3 113190 91497 0 0
T4 63765 48993 0 0
T5 82229 70527 0 0
T6 90093 87546 0 0
T11 117918 105972 0 0
T12 21177 19041 0 0
T13 119394 98991 0 0
T14 101343 83277 0 0

Line Coverage for Instance : tb.dut.u_prim_lc_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 797 797 0 0
OutputsKnown_A 54237172 51208049 0 0
gen_no_flops.OutputDelay_A 54237172 51208049 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 797 797 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 54237172 51208049 0 0
T1 66323 66269 0 0
T2 2104 2009 0 0
T3 37730 30499 0 0
T4 21255 16331 0 0
T5 32857 28522 0 0
T6 30031 29182 0 0
T11 39306 35324 0 0
T12 7059 6347 0 0
T13 39798 32997 0 0
T14 33781 27759 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 54237172 51208049 0 0
T1 66323 66269 0 0
T2 2104 2009 0 0
T3 37730 30499 0 0
T4 21255 16331 0 0
T5 32857 28522 0 0
T6 30031 29182 0 0
T11 39306 35324 0 0
T12 7059 6347 0 0
T13 39798 32997 0 0
T14 33781 27759 0 0

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack
Line No.TotalCoveredPercent
TOTAL55100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 4 4


Assert Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 797 797 0 0
OutputsKnown_A 53950359 50979413 0 0
gen_flops.OutputDelay_A 53950359 50860607 0 2352


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 797 797 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 53950359 50979413 0 0
T1 66323 66269 0 0
T2 2104 2009 0 0
T3 37730 30499 0 0
T4 21255 16331 0 0
T5 29063 25518 0 0
T6 30031 29182 0 0
T11 39306 35324 0 0
T12 7059 6347 0 0
T13 39798 32997 0 0
T14 33781 27759 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 53950359 50860607 0 2352
T1 66323 66266 0 3
T2 2104 2006 0 3
T3 37730 30211 0 3
T4 21255 16127 0 3
T5 29063 25374 0 0
T6 30031 29149 0 3
T11 39306 35165 0 3
T12 7059 6317 0 3
T13 39798 32727 0 3
T14 33781 27516 0 3
T23 0 0 0 3

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 797 797 0 0
OutputsKnown_A 53858916 50890258 0 0
gen_flops.OutputDelay_A 53858916 50771518 0 2352


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 797 797 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 53858916 50890258 0 0
T1 66323 66269 0 0
T2 2104 2009 0 0
T3 37730 30499 0 0
T4 21255 16331 0 0
T5 25306 21895 0 0
T6 30031 29182 0 0
T11 39306 35324 0 0
T12 7059 6347 0 0
T13 39798 32997 0 0
T14 33781 27759 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 53858916 50771518 0 2352
T1 66323 66266 0 3
T2 2104 2006 0 3
T3 37730 30211 0 3
T4 21255 16127 0 3
T5 25306 21754 0 3
T6 30031 29149 0 3
T11 39306 35165 0 3
T12 7059 6317 0 3
T13 39798 32727 0 3
T14 33781 27516 0 3

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid
Line No.TotalCoveredPercent
TOTAL55100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 4 4


Assert Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 797 797 0 0
OutputsKnown_A 53852585 50878273 0 0
gen_no_flops.OutputDelay_A 53852585 50878273 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 797 797 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 53852585 50878273 0 0
T1 66323 66269 0 0
T2 2104 2009 0 0
T3 37730 30499 0 0
T4 21255 16331 0 0
T5 24021 20423 0 0
T6 30031 29182 0 0
T11 39306 35324 0 0
T12 7059 6347 0 0
T13 39798 32997 0 0
T14 33781 27759 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 53852585 50878273 0 0
T1 66323 66269 0 0
T2 2104 2009 0 0
T3 37730 30499 0 0
T4 21255 16331 0 0
T5 24021 20423 0 0
T6 30031 29182 0 0
T11 39306 35324 0 0
T12 7059 6347 0 0
T13 39798 32997 0 0
T14 33781 27759 0 0

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 8 8


Assert Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 797 797 0 0
OutputsKnown_A 53857958 50883327 0 0
gen_no_flops.OutputDelay_A 53857958 50883327 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 797 797 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 53857958 50883327 0 0
T1 66323 66269 0 0
T2 2104 2009 0 0
T3 37730 30499 0 0
T4 21255 16331 0 0
T5 25351 21582 0 0
T6 30031 29182 0 0
T11 39306 35324 0 0
T12 7059 6347 0 0
T13 39798 32997 0 0
T14 33781 27759 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 53857958 50883327 0 0
T1 66323 66269 0 0
T2 2104 2009 0 0
T3 37730 30499 0 0
T4 21255 16331 0 0
T5 25351 21582 0 0
T6 30031 29182 0 0
T11 39306 35324 0 0
T12 7059 6347 0 0
T13 39798 32997 0 0
T14 33781 27759 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%