Unified Coverage Report :: Module :: lc_ctrl

Module : lc_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.52	100.00	81.94	98.16		100.00	87.50

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	93.75	100.00	83.10	98.16		100.00	87.50

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	83.10	98.16		100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.27	97.29	95.78	91.98	97.67	96.13	98.73

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_alert_tx[2].u_prim_alert_sender	100.00			100.00
lc_ctrl_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_dmi_jtag	95.82			95.82
u_lc_ctrl_fsm	96.58	98.86	90.77		100.00	96.12	97.14
u_lc_ctrl_kmac_if	95.42	98.21	100.00		83.33	95.56	100.00
u_prim_clock_mux2	85.19	100.00	55.56				100.00
u_prim_esc_receiver0	16.07			16.07
u_prim_esc_receiver1	16.07			16.07
u_prim_flop_2sync_init	100.00	100.00				100.00
u_prim_lc_sync	100.00	100.00					100.00
u_prim_mubi4_dec	0.00	0.00
u_prim_rst_n_mux2	85.19	100.00	55.56				100.00
u_reg	99.29	97.79	98.66	100.00		100.00	100.00
u_reg_tap	87.03	95.78	97.97	50.24		91.18	100.00
u_tap_tlul_host	77.17	96.08	92.86	6.90		90.00	100.00

Line Coverage for Module : lc_ctrl

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
ALWAYS	313	41	41	100.00
ALWAYS	364	41	41	100.00
ALWAYS	462	33	33	100.00
ALWAYS	521	3	3	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	563	1	1	100.00
CONT_ASSIGN	569	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
ALWAYS	664	5	5	100.00
CONT_ASSIGN	673	1	1	100.00
CONT_ASSIGN	674	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
211	1	1
264	1	1
313	1	1
314	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
333	1	1
334	1	1
337	1	1
340	1	1
341	1	1
342	1	1
343	1	1
344	1	1
345	1	1
346	1	1
348	1	1
349	1	1
350	1	1
351	1	1
352	1	1
353	1	1
354	1	1
355	1	1
357	1	1
358	1	1
359	1	1
			MISSING_ELSE
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
370	1	1
371	1	1
376	1	1
378	1	1
380	1	1
382	1	1
			MISSING_ELSE
387	1	1
389	1	1
390	1	1
393	1	1
394	1	1
			MISSING_ELSE
402	1	1
403	1	1
			MISSING_ELSE
407	1	1
408	1	1
409	1	1
			MISSING_ELSE
413	1	1
414	1	1
415	1	1
			MISSING_ELSE
420	1	1
421	1	1
			MISSING_ELSE
423	1	1
424	1	1
427	1	1
428	1	1
			MISSING_ELSE
436	1	1
437	1	1
			MISSING_ELSE
441	1	1
442	1	1
443	1	1
			MISSING_ELSE
447	1	1
448	1	1
449	1	1
			MISSING_ELSE
454	1	1
455	1	1
			MISSING_ELSE
			MISSING_ELSE
			MISSING_ELSE
462	1	1
463	1	1
464	1	1
465	1	1
466	1	1
467	1	1
468	1	1
469	1	1
470	1	1
471	1	1
472	1	1
473	1	1
474	1	1
475	1	1
476	1	1
477	1	1
487	1	1
488	1	1
490	1	1
493	1	1
494	1	1
495	1	1
496	1	1
497	1	1
498	1	1
499	1	1
500	1	1
504	1	1
505	1	1
506	1	1
507	1	1
508	1	1
509	1	1
521	1	1
522	1	1
524	1	1
534	1	1
550	1	1
552	1	1
563	1	1
569	1	1
578	1	1
664	1	1
665	1	1
666	1	1
668	1	1
669	1	1
673	1	1
674	1	1

---

Cond Coverage for Module : lc_ctrl

	Total	Covered	Percent
Conditions	72	59	81.94
Logical	72	59	81.94
Non-Logical	0	0
Event	0	0

 LINE       211
 EXPRESSION (dmi_req_ready & dmi_resp_ready)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T7

 LINE       238
 EXPRESSION (dmi_req_valid & dmi_resp_ready)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Not Covered
1	1	Covered	T1,T6,T7

 LINE       238
 EXPRESSION (dmi_req.op == DTM_WRITE)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       390
 EXPRESSION (tap_reg2hw.transition_cmd.q & tap_reg2hw.transition_cmd.qe)
             -------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T7
1	1	Covered	T6,T7,T17

 LINE       424
 EXPRESSION (reg2hw.transition_cmd.q & reg2hw.transition_cmd.qe)
             -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T4,T5,T11

 LINE       487
 EXPRESSION (SecVolatileRawUnlockEn && transition_cmd && ((!volatile_raw_unlock_q)))
             -----------1----------    -------2------    -------------3------------

-1-	-2-	-3-	Status	Tests
-	0	1	Covered	T1,T2,T3
-	1	0	Covered	T31,T32,T33
-	1	1	Covered	T4,T5,T11

 LINE       490
 EXPRESSION (trans_success_d | trans_success_q)
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T13
1	0	Covered	T5,T6,T13

 LINE       493
 EXPRESSION (trans_cnt_oflw_error_d | trans_cnt_oflw_error_q)
             -----------1----------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T7,T19
1	0	Covered	T15,T7,T19

 LINE       494
 EXPRESSION (trans_invalid_error_d | trans_invalid_error_q)
             ----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T15,T7
1	0	Covered	T1,T15,T7

 LINE       495
 EXPRESSION (token_invalid_error_d | token_invalid_error_q)
             ----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T7
1	0	Covered	T5,T15,T7

 LINE       496
 EXPRESSION (flash_rma_error_d | flash_rma_error_q)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T7
1	0	Covered	T5,T15,T7

 LINE       497
 EXPRESSION (otp_prog_error_d | fatal_prog_error_q)
             --------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T15
1	0	Covered	T5,T12,T15

 LINE       498
 EXPRESSION (state_invalid_error_d | fatal_state_error_q)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T5,T6

 LINE       499
 EXPRESSION (otp_lc_data_i.error | otp_part_error_q)
             ---------1---------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T19,T21,T44
1	0	Covered	T15,T7,T19

 LINE       500
 EXPRESSION (fatal_bus_integ_error_csr_d | fatal_bus_integ_error_tap_d | fatal_bus_integ_error_q)
             -------------1-------------   -------------2-------------   -----------3-----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T66,T95,T96
1	0	0	Covered	T66,T95,T96

 LINE       569
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T97,T98
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T97,T98

 LINE       569
 SUB-EXPRESSION (reg2hw.alert_test.fatal_state_error.q & reg2hw.alert_test.fatal_state_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T97,T98
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T97,T98

 LINE       569
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prog_error.q & reg2hw.alert_test.fatal_prog_error.qe)
                 ------------------1-----------------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T97,T98
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T97,T98

 LINE       578
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_bus_integ_error.q & tap_reg2hw.alert_test.fatal_bus_integ_error.qe)
                 ----------------------1----------------------   -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T7
1	1	Not Covered

 LINE       578
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_state_error.q & tap_reg2hw.alert_test.fatal_state_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T7
1	1	Not Covered

 LINE       578
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_prog_error.q & tap_reg2hw.alert_test.fatal_prog_error.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T7
1	1	Not Covered

 LINE       591
 EXPRESSION (alert_test[0] | tap_alert_test[0])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T97,T98

 LINE       591
 EXPRESSION (alert_test[1] | tap_alert_test[1])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T97,T98

 LINE       591
 EXPRESSION (alert_test[2] | tap_alert_test[2])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T97,T98

---

Toggle Coverage for Module : lc_ctrl

	Total	Covered	Percent
Totals	106	100	94.34
Total Bits	7434	7297	98.16
Total Bits 0->1	3717	3649	98.17
Total Bits 1->0	3717	3648	98.14

Ports	106	100	94.34
Port Bits	7434	7297	98.16
Port Bits 0->1	3717	3649	98.17
Port Bits 1->0	3717	3648	98.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	INPUT
rst_ni	Yes	Yes	T90,T92,T94	Yes	T60,T86,T87	INPUT
clk_kmac_i	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	INPUT
rst_kmac_ni	Yes	Yes	T90,T92,T94	Yes	T60,T86,T87	INPUT
tl_i.d_ready	Yes	Yes	T86,T90,T91	Yes	T60,T86,T87	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T60,T88,T89	Yes	T60,T86,T88	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T60,T88,T89	Yes	T60,T86,T87	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T86,T89,T92	Yes	T89,T92,T93	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T60,T88,T89	Yes	T60,T88,T89	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T60,T89,T92	Yes	T60,T86,T89	INPUT
tl_i.a_address[31:0]	Yes	Yes	T60,T86,T87	Yes	T60,T89,T92	INPUT
tl_i.a_source[7:0]	Yes	Yes	T60,T88,T89	Yes	T60,T88,T89	INPUT
tl_i.a_size[1:0]	Yes	Yes	T60,T86,T89	Yes	T60,T89,T92	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T60,T86,T88	Yes	T60,T88,T89	INPUT
tl_i.a_valid	Yes	Yes	T60,T88,T89	Yes	T60,T88,T89	INPUT
tl_o.a_ready	Yes	Yes	T60,T88,T89	Yes	T60,T88,T89	OUTPUT
tl_o.d_error	Yes	Yes	T92,T94,T99	Yes	T89,T92,T93	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T60,T88,T92	Yes	T60,T88,T92	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T60,*T88,*T89	Yes	T60,T88,T89	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T60,T88,T92	Yes	T60,T88,T89	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T60,T88,T89	Yes	T60,T88,T89	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T60,T89,T92	Yes	T60,T89,T92	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T60,*T88,*T89	Yes	T60,T88,T89	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T60,T88,T89	Yes	T60,T88,T89	OUTPUT
jtag_i.tdi	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	INPUT
jtag_i.trst_n	Yes	Yes	T90,T92,T94	Yes	T60,T86,T87	INPUT
jtag_i.tms	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	INPUT
jtag_i.tck	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	INPUT
jtag_o.tdo_oe	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	OUTPUT
jtag_o.tdo	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	OUTPUT
scan_rst_ni	Yes	Yes	T1,T8,T9	Yes	T1,T8,T10	INPUT
scanmode_i[3:0]	No	No		No		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T60,T86,T88	Yes	T60,T86,T88	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T86,T87,T88	Yes	T86,T87,T88	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T60,T86,T88	Yes	T60,T86,T88	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T60,T86,T88	Yes	T60,T86,T88	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T86,T87,T88	Yes	T86,T87,T88	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T60,T86,T88	Yes	T60,T86,T88	OUTPUT
esc_scrap_state0_tx_i.resp_n	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
esc_scrap_state0_tx_i.resp_p	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
esc_scrap_state0_rx_o.esc_n	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
esc_scrap_state0_rx_o.esc_p	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
esc_scrap_state1_tx_i.resp_n	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
esc_scrap_state1_tx_i.resp_p	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
esc_scrap_state1_rx_o.esc_n	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
esc_scrap_state1_rx_o.esc_p	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
pwr_lc_i.lc_init	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	INPUT
pwr_lc_o.lc_idle	Yes	Yes	T88,T90,T92	Yes	T60,T86,T87	OUTPUT
pwr_lc_o.lc_done	Yes	Yes	T90,T92,T94	Yes	T60,T86,T87	OUTPUT
strap_en_override_o	No	No		Yes	T31,T32,T33	OUTPUT
lc_otp_vendor_test_o.ctrl[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
lc_otp_vendor_test_i.status[31:0]	Yes	Yes	T90,T92,T99	Yes	T89,T90,T92	INPUT
lc_otp_program_o.count[383:0]	Yes	Yes	T3,T7,T16	Yes	T3,T7,T16	OUTPUT
lc_otp_program_o.state[319:0]	Yes	Yes	T3,T16,T85	Yes	T3,T16,T85	OUTPUT
lc_otp_program_o.req	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
lc_otp_program_i.ack	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
lc_otp_program_i.err	Yes	Yes	T7,T21,T39	Yes	T7,T21,T39	INPUT
kmac_data_i.error	Yes	Yes	T15,T7,T19	Yes	T15,T7,T19	INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
kmac_data_i.done	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
kmac_data_i.ready	Yes	Yes	T89,T90,T92	Yes	T60,T86,T87	INPUT
kmac_data_o.last	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
kmac_data_o.strb[7:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
kmac_data_o.data[63:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
kmac_data_o.valid	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
otp_lc_data_i.rma_token[127:0]	Yes	Yes	T92,T100,T101	Yes	T92,T101,T102	INPUT
otp_lc_data_i.rma_token_valid[3:0]	Yes	Yes	T5,T47,T54	Yes	T5,T47,T54	INPUT
otp_lc_data_i.test_exit_token[127:0]	Yes	Yes	T92,T100,T103	Yes	T92,T99,T104	INPUT
otp_lc_data_i.test_unlock_token[127:0]	Yes	Yes	T92,T99,T104	Yes	T92,T94,T100	INPUT
otp_lc_data_i.test_tokens_valid[3:0]	Yes	Yes	T5,T47,T54	Yes	T5,T47,T54	INPUT
otp_lc_data_i.secrets_valid[3:0]	Yes	Yes	T5,T47,T54	Yes	T5,T47,T54	INPUT
otp_lc_data_i.count[383:0]	Yes	Yes	T3,T7,T16	Yes	T3,T7,T16	INPUT
otp_lc_data_i.state[319:0]	Yes	Yes	T3,T16,T85	Yes	T3,T16,T85	INPUT
otp_lc_data_i.error	Yes	Yes	T15,T7,T19	Yes	T15,T7,T19	INPUT
otp_lc_data_i.valid	Yes	Yes	T3,T16,T20	Yes	T3,T16,T20	INPUT
lc_dft_en_o[3:0]	Yes	Yes	T90,T92,T94	Yes	T87,T90,T92	OUTPUT
lc_nvm_debug_en_o[3:0]	Yes	Yes	T90,T92,T94	Yes	T87,T90,T92	OUTPUT
lc_hw_debug_en_o[3:0]	Yes	Yes	T90,T92,T94	Yes	T87,T90,T92	OUTPUT
lc_cpu_en_o[3:0]	Yes	Yes	T90,T92,T94	Yes	T60,T87,T90	OUTPUT
lc_creator_seed_sw_rw_en_o[3:0]	Yes	Yes	T92,T94,T99	Yes	T60,T92,T93	OUTPUT
lc_owner_seed_sw_rw_en_o[3:0]	Yes	Yes	T92,T94,T99	Yes	T60,T92,T93	OUTPUT
lc_iso_part_sw_rd_en_o[3:0]	Yes	Yes	T92,T94,T103	Yes	T60,T92,T94	OUTPUT
lc_iso_part_sw_wr_en_o[3:0]	Yes	Yes	T90,T92,T94	Yes	T60,T87,T90	OUTPUT
lc_seed_hw_rd_en_o[3:0]	Yes	Yes	T92,T105,T106	Yes	T92,T107,T108	OUTPUT
lc_keymgr_en_o[3:0]	Yes	Yes	T92,T94,T99	Yes	T60,T92,T93	OUTPUT
lc_escalate_en_o[3:0]	Yes	Yes	T109,T110,T106	Yes	T88,T109,T110	OUTPUT
lc_check_byp_en_o[3:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
lc_clk_byp_req_o[3:0]	Yes	Yes	T7,T43,T21	Yes	T1,T7,T32	OUTPUT
lc_clk_byp_ack_i[3:0]	Yes	Yes	T5,T15,T7	Yes	T5,T15,T7	INPUT
lc_flash_rma_seed_o[31:0]	Yes	Yes	T1,T4,T5	Yes	T111,T1,T4	OUTPUT
lc_flash_rma_req_o[3:0]	Yes	Yes	T5,T6,T13	Yes	T5,T6,T13	OUTPUT
lc_flash_rma_ack_i[3:0]	Yes	Yes	T5,T6,T13	Yes	T5,T6,T13	INPUT
lc_keymgr_div_o[127:0]	Yes	Yes	T92,T94,T103	Yes	T60,T92,T94	OUTPUT
otp_device_id_i[255:0]	Yes	Yes	T90,T100,T112	Yes	T90,T93,T113	INPUT
otp_manuf_state_i[255:0]	Yes	Yes	T90,T92,T103	Yes	T87,T90,T91	INPUT
hw_rev_o.reserved[23:0]	No	No		No		OUTPUT
hw_rev_o.revision_id[7:0]	No	No		No		OUTPUT
hw_rev_o.product_id[15:0]	No	No		No		OUTPUT
hw_rev_o.silicon_creator_id[15:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : lc_ctrl

	Line No.	Total	Covered	Percent
Branches		31	31	100.00
IF	342	3	3	100.00
IF	376	3	3	100.00
IF	387	18	18	100.00
IF	462	3	3	100.00
IF	664	2	2	100.00
IF	521	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	342	if (prim_mubi_pkg::mubi8_test_true_strict(tap_claim_transition_if_q))
-2-:	351	if (prim_mubi_pkg::mubi8_test_true_strict(sw_claim_transition_if_q))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T6,T7
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	376	if ((prim_mubi_pkg::mubi8_test_false_loose(sw_claim_transition_if_q) && tap_reg2hw.claim_transition_if.qe))
-2-:	380	if ((prim_mubi_pkg::mubi8_test_false_loose(tap_claim_transition_if_q) && reg2hw.claim_transition_if.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T6,T7
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	387	if (lc_idle_d)
-2-:	389	if (prim_mubi_pkg::mubi8_test_true_strict(tap_claim_transition_if_q))
-3-:	393	if (tap_reg2hw.transition_ctrl.ext_clock_en.qe)
-4-:	402	if (tap_reg2hw.transition_ctrl.volatile_raw_unlock.qe)
-5-:	413	if (tap_reg2hw.transition_target.qe)
-6-:	420	if (tap_reg2hw.otp_vendor_test_ctrl.qe)
-7-:	423	if (prim_mubi_pkg::mubi8_test_true_strict(sw_claim_transition_if_q))
-8-:	427	if (reg2hw.transition_ctrl.ext_clock_en.qe)
-9-:	436	if (reg2hw.transition_ctrl.volatile_raw_unlock.qe)
-10-:	447	if (reg2hw.transition_target.qe)
-11-:	454	if (reg2hw.otp_vendor_test_ctrl.qe)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
1	1	1	-	-	-	-	-	-	-	-	Covered	T1,T22,T114
1	1	0	-	-	-	-	-	-	-	-	Covered	T1,T6,T7
1	1	-	1	-	-	-	-	-	-	-	Covered	T1,T22,T114
1	1	-	0	-	-	-	-	-	-	-	Covered	T1,T6,T7
1	1	-	-	1	-	-	-	-	-	-	Covered	T1,T6,T7
1	1	-	-	0	-	-	-	-	-	-	Covered	T1,T6,T7
1	1	-	-	-	1	-	-	-	-	-	Covered	T1,T6,T7
1	1	-	-	-	0	-	-	-	-	-	Covered	T1,T6,T7
1	0	-	-	-	-	1	1	-	-	-	Covered	T1,T7,T31
1	0	-	-	-	-	1	0	-	-	-	Covered	T1,T3,T4
1	0	-	-	-	-	1	-	1	-	-	Covered	T1,T7,T31
1	0	-	-	-	-	1	-	0	-	-	Covered	T1,T3,T4
1	0	-	-	-	-	1	-	-	1	-	Covered	T1,T4,T5
1	0	-	-	-	-	1	-	-	0	-	Covered	T1,T3,T4
1	0	-	-	-	-	1	-	-	-	1	Covered	T1,T4,T5
1	0	-	-	-	-	1	-	-	-	0	Covered	T1,T3,T4
1	0	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	462	if ((!rst_ni))
-2-:	487	if (((SecVolatileRawUnlockEn && transition_cmd) && (!volatile_raw_unlock_q)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T11
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	664	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	521	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : lc_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	28	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	28	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	54237172	51208049	0	0
DecLcCountWidthCheck_A	797	797	0	0
DecLcIdStateWidthCheck_A	797	797	0	0
DecLcStateWidthCheck_A	797	797	0	0
FpvSecCmCtrlKmacIfFsmCheck_A	52918115	0	0	0
FpvSecCmCtrlLcCntCheck_A	50238239	1	0	0
FpvSecCmCtrlLcFsmCheck_A	52961868	0	0	0
FpvSecCmCtrlLcStateCheck_A	50928824	0	0	0
FpvSecCmRegWeOnehotCheck_A	54237172	80	0	0
FpvSecCmTapRegWeOnehotCheck_A	54237172	0	0	0
LcCheckBypassEnKnown_A	54237172	51208049	0	0
LcClkBypReqKnown_A	54237172	51208049	0	0
LcCpuEnKnown_A	54237172	51208049	0	0
LcCreatorSwRwEn_A	54237172	51208049	0	0
LcDftEnKnown_A	54237172	51208049	0	0
LcEscalateEnKnown_A	54237172	51208049	0	0
LcFlashRmaReqKnown_A	54237172	51208049	0	0
LcFlashRmaSeedKnown_A	54237172	51208049	0	0
LcHwDebugEnKnown_A	54237172	51208049	0	0
LcIsoSwRwEn_A	54237172	51208049	0	0
LcIsoSwWrEn_A	54237172	51208049	0	0
LcKeymgrDiv_A	54237172	51208049	0	0
LcKeymgrEnKnown_A	54237172	51208049	0	0
LcNvmDebugEnKnown_A	54237172	51208049	0	0
LcOtpProgramKnown_A	54237172	51208049	0	0
LcOtpTokenKnown_A	54237172	51208049	0	0
LcOwnerSwRwEn_A	54237172	51208049	0	0
LcSeedHwRdEn_A	54237172	51208049	0	0
NumTokenWordsCheck_A	797	797	0	0
OtpTestCtrlWidth_A	797	797	0	0
PwrLcKnown_A	54237172	51208049	0	0
TlOKnown	54237172	51208049	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

DecLcCountWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797	797	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

DecLcIdStateWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797	797	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

DecLcStateWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797	797	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

FpvSecCmCtrlKmacIfFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52918115	0	0	0

FpvSecCmCtrlLcCntCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50238239	1	0	0
T115	714897	1	0	0
T116	19354	0	0	0
T117	31180	0	0	0
T118	9370	0	0	0
T119	75767	0	0	0
T120	9165	0	0	0
T121	1007	0	0	0
T122	32566	0	0	0
T123	30395	0	0	0
T124	38540	0	0	0

FpvSecCmCtrlLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52961868	0	0	0

FpvSecCmCtrlLcStateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50928824	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	80	0	0
T62	35416	0	0	0
T66	20055	20	0	0
T95	0	20	0	0
T96	0	20	0	0
T125	0	10	0	0
T126	0	10	0	0
T127	28425	0	0	0
T128	375516	0	0	0
T129	36791	0	0	0
T130	1704	0	0	0
T131	9974	0	0	0
T132	34699	0	0	0
T133	87764	0	0	0
T134	76706	0	0	0

FpvSecCmTapRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	0	0	0

LcCheckBypassEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcClkBypReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcCpuEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcCreatorSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcDftEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcEscalateEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcFlashRmaReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcFlashRmaSeedKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcHwDebugEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcIsoSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcIsoSwWrEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcKeymgrDiv_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcKeymgrEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcNvmDebugEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcOtpProgramKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcOtpTokenKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcOwnerSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcSeedHwRdEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

NumTokenWordsCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797	797	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpTestCtrlWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797	797	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

PwrLcKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

TlOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
ALWAYS	313	41	41	100.00
ALWAYS	364	41	41	100.00
ALWAYS	462	33	33	100.00
ALWAYS	521	3	3	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	563	1	1	100.00
CONT_ASSIGN	569	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
ALWAYS	664	5	5	100.00
CONT_ASSIGN	673	1	1	100.00
CONT_ASSIGN	674	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
211	1	1
264	1	1
313	1	1
314	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
333	1	1
334	1	1
337	1	1
340	1	1
341	1	1
342	1	1
343	1	1
344	1	1
345	1	1
346	1	1
348	1	1
349	1	1
350	1	1
351	1	1
352	1	1
353	1	1
354	1	1
355	1	1
357	1	1
358	1	1
359	1	1
			MISSING_ELSE
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
370	1	1
371	1	1
376	1	1
378	1	1
380	1	1
382	1	1
			MISSING_ELSE
387	1	1
389	1	1
390	1	1
393	1	1
394	1	1
			MISSING_ELSE
402	1	1
403	1	1
			MISSING_ELSE
407	1	1
408	1	1
409	1	1
			MISSING_ELSE
413	1	1
414	1	1
415	1	1
			MISSING_ELSE
420	1	1
421	1	1
			MISSING_ELSE
423	1	1
424	1	1
427	1	1
428	1	1
			MISSING_ELSE
436	1	1
437	1	1
			MISSING_ELSE
441	1	1
442	1	1
443	1	1
			MISSING_ELSE
447	1	1
448	1	1
449	1	1
			MISSING_ELSE
454	1	1
455	1	1
			MISSING_ELSE
			MISSING_ELSE
			MISSING_ELSE
462	1	1
463	1	1
464	1	1
465	1	1
466	1	1
467	1	1
468	1	1
469	1	1
470	1	1
471	1	1
472	1	1
473	1	1
474	1	1
475	1	1
476	1	1
477	1	1
487	1	1
488	1	1
490	1	1
493	1	1
494	1	1
495	1	1
496	1	1
497	1	1
498	1	1
499	1	1
500	1	1
504	1	1
505	1	1
506	1	1
507	1	1
508	1	1
509	1	1
521	1	1
522	1	1
524	1	1
534	1	1
550	1	1
552	1	1
563	1	1
569	1	1
578	1	1
664	1	1
665	1	1
666	1	1
668	1	1
669	1	1
673	1	1
674	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	71	59	83.10
Logical	71	59	83.10
Non-Logical	0	0
Event	0	0

 LINE       211
 EXPRESSION (dmi_req_ready & dmi_resp_ready)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T7

 LINE       238
 EXPRESSION (dmi_req_valid & dmi_resp_ready)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Not Covered
1	1	Covered	T1,T6,T7

 LINE       238
 EXPRESSION (dmi_req.op == DTM_WRITE)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       390
 EXPRESSION (tap_reg2hw.transition_cmd.q & tap_reg2hw.transition_cmd.qe)
             -------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T7
1	1	Covered	T6,T7,T17

 LINE       424
 EXPRESSION (reg2hw.transition_cmd.q & reg2hw.transition_cmd.qe)
             -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T4,T5,T11

 LINE       487
 EXPRESSION (SecVolatileRawUnlockEn && transition_cmd && ((!volatile_raw_unlock_q)))
             -----------1----------    -------2------    -------------3------------

-1-	-2-	-3-	Status	Tests
-	0	1	Covered	T1,T2,T3
-	1	0	Covered	T31,T32,T33
-	1	1	Covered	T4,T5,T11

 LINE       490
 EXPRESSION (trans_success_d | trans_success_q)
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T13
1	0	Covered	T5,T6,T13

 LINE       493
 EXPRESSION (trans_cnt_oflw_error_d | trans_cnt_oflw_error_q)
             -----------1----------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T7,T19
1	0	Covered	T15,T7,T19

 LINE       494
 EXPRESSION (trans_invalid_error_d | trans_invalid_error_q)
             ----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T15,T7
1	0	Covered	T1,T15,T7

 LINE       495
 EXPRESSION (token_invalid_error_d | token_invalid_error_q)
             ----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T7
1	0	Covered	T5,T15,T7

 LINE       496
 EXPRESSION (flash_rma_error_d | flash_rma_error_q)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T7
1	0	Covered	T5,T15,T7

 LINE       497
 EXPRESSION (otp_prog_error_d | fatal_prog_error_q)
             --------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T15
1	0	Covered	T5,T12,T15

 LINE       498
 EXPRESSION (state_invalid_error_d | fatal_state_error_q)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T5,T6

 LINE       499
 EXPRESSION (otp_lc_data_i.error | otp_part_error_q)
             ---------1---------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T19,T21,T44
1	0	Covered	T15,T7,T19

 LINE       500
 EXPRESSION (fatal_bus_integ_error_csr_d | fatal_bus_integ_error_tap_d | fatal_bus_integ_error_q)
             -------------1-------------   -------------2-------------   -----------3-----------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Covered	T1,T2,T3
0	0	1	Excluded		VC_COV_UNR
0	1	0	Covered	T66,T95,T96
1	0	0	Covered	T66,T95,T96

 LINE       569
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T97,T98
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T97,T98

 LINE       569
 SUB-EXPRESSION (reg2hw.alert_test.fatal_state_error.q & reg2hw.alert_test.fatal_state_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T97,T98
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T97,T98

 LINE       569
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prog_error.q & reg2hw.alert_test.fatal_prog_error.qe)
                 ------------------1-----------------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T97,T98
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T97,T98

 LINE       578
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_bus_integ_error.q & tap_reg2hw.alert_test.fatal_bus_integ_error.qe)
                 ----------------------1----------------------   -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T7
1	1	Not Covered

 LINE       578
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_state_error.q & tap_reg2hw.alert_test.fatal_state_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T7
1	1	Not Covered

 LINE       578
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_prog_error.q & tap_reg2hw.alert_test.fatal_prog_error.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T7
1	1	Not Covered

 LINE       591
 EXPRESSION (alert_test[0] | tap_alert_test[0])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T97,T98

 LINE       591
 EXPRESSION (alert_test[1] | tap_alert_test[1])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T97,T98

 LINE       591
 EXPRESSION (alert_test[2] | tap_alert_test[2])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T97,T98

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	106	100	94.34
Total Bits	7434	7297	98.16
Total Bits 0->1	3717	3649	98.17
Total Bits 1->0	3717	3648	98.14

Ports	106	100	94.34
Port Bits	7434	7297	98.16
Port Bits 0->1	3717	3649	98.17
Port Bits 1->0	3717	3648	98.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	INPUT
rst_ni	Yes	Yes	T90,T92,T94	Yes	T60,T86,T87	INPUT
clk_kmac_i	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	INPUT
rst_kmac_ni	Yes	Yes	T90,T92,T94	Yes	T60,T86,T87	INPUT
tl_i.d_ready	Yes	Yes	T86,T90,T91	Yes	T60,T86,T87	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T60,T88,T89	Yes	T60,T86,T88	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T60,T88,T89	Yes	T60,T86,T87	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T86,T89,T92	Yes	T89,T92,T93	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T60,T88,T89	Yes	T60,T88,T89	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T60,T89,T92	Yes	T60,T86,T89	INPUT
tl_i.a_address[31:0]	Yes	Yes	T60,T86,T87	Yes	T60,T89,T92	INPUT
tl_i.a_source[7:0]	Yes	Yes	T60,T88,T89	Yes	T60,T88,T89	INPUT
tl_i.a_size[1:0]	Yes	Yes	T60,T86,T89	Yes	T60,T89,T92	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T60,T86,T88	Yes	T60,T88,T89	INPUT
tl_i.a_valid	Yes	Yes	T60,T88,T89	Yes	T60,T88,T89	INPUT
tl_o.a_ready	Yes	Yes	T60,T88,T89	Yes	T60,T88,T89	OUTPUT
tl_o.d_error	Yes	Yes	T92,T94,T99	Yes	T89,T92,T93	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T60,T88,T92	Yes	T60,T88,T92	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T60,*T88,*T89	Yes	T60,T88,T89	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T60,T88,T92	Yes	T60,T88,T89	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T60,T88,T89	Yes	T60,T88,T89	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T60,T89,T92	Yes	T60,T89,T92	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T60,*T88,*T89	Yes	T60,T88,T89	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T60,T88,T89	Yes	T60,T88,T89	OUTPUT
jtag_i.tdi	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	INPUT
jtag_i.trst_n	Yes	Yes	T90,T92,T94	Yes	T60,T86,T87	INPUT
jtag_i.tms	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	INPUT
jtag_i.tck	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	INPUT
jtag_o.tdo_oe	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	OUTPUT
jtag_o.tdo	Yes	Yes	T86,T87,T90	Yes	T86,T87,T90	OUTPUT
scan_rst_ni	Yes	Yes	T1,T8,T9	Yes	T1,T8,T10	INPUT
scanmode_i[3:0]	No	No		No		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T60,T86,T88	Yes	T60,T86,T88	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T86,T87,T88	Yes	T86,T87,T88	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T60,T86,T88	Yes	T60,T86,T88	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T60,T86,T88	Yes	T60,T86,T88	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T86,T87,T88	Yes	T86,T87,T88	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T60,T86,T88	Yes	T60,T86,T88	OUTPUT
esc_scrap_state0_tx_i.resp_n	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
esc_scrap_state0_tx_i.resp_p	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
esc_scrap_state0_rx_o.esc_n	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
esc_scrap_state0_rx_o.esc_p	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
esc_scrap_state1_tx_i.resp_n	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
esc_scrap_state1_tx_i.resp_p	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
esc_scrap_state1_rx_o.esc_n	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
esc_scrap_state1_rx_o.esc_p	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
pwr_lc_i.lc_init	Yes	Yes	T60,T86,T87	Yes	T60,T86,T87	INPUT
pwr_lc_o.lc_idle	Yes	Yes	T88,T90,T92	Yes	T60,T86,T87	OUTPUT
pwr_lc_o.lc_done	Yes	Yes	T90,T92,T94	Yes	T60,T86,T87	OUTPUT
strap_en_override_o	No	No		Yes	T31,T32,T33	OUTPUT
lc_otp_vendor_test_o.ctrl[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
lc_otp_vendor_test_i.status[31:0]	Yes	Yes	T90,T92,T99	Yes	T89,T90,T92	INPUT
lc_otp_program_o.count[383:0]	Yes	Yes	T3,T7,T16	Yes	T3,T7,T16	OUTPUT
lc_otp_program_o.state[319:0]	Yes	Yes	T3,T16,T85	Yes	T3,T16,T85	OUTPUT
lc_otp_program_o.req	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
lc_otp_program_i.ack	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
lc_otp_program_i.err	Yes	Yes	T7,T21,T39	Yes	T7,T21,T39	INPUT
kmac_data_i.error	Yes	Yes	T15,T7,T19	Yes	T15,T7,T19	INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
kmac_data_i.done	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
kmac_data_i.ready	Yes	Yes	T89,T90,T92	Yes	T60,T86,T87	INPUT
kmac_data_o.last	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
kmac_data_o.strb[7:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
kmac_data_o.data[63:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
kmac_data_o.valid	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
otp_lc_data_i.rma_token[127:0]	Yes	Yes	T92,T100,T101	Yes	T92,T101,T102	INPUT
otp_lc_data_i.rma_token_valid[3:0]	Yes	Yes	T5,T47,T54	Yes	T5,T47,T54	INPUT
otp_lc_data_i.test_exit_token[127:0]	Yes	Yes	T92,T100,T103	Yes	T92,T99,T104	INPUT
otp_lc_data_i.test_unlock_token[127:0]	Yes	Yes	T92,T99,T104	Yes	T92,T94,T100	INPUT
otp_lc_data_i.test_tokens_valid[3:0]	Yes	Yes	T5,T47,T54	Yes	T5,T47,T54	INPUT
otp_lc_data_i.secrets_valid[3:0]	Yes	Yes	T5,T47,T54	Yes	T5,T47,T54	INPUT
otp_lc_data_i.count[383:0]	Yes	Yes	T3,T7,T16	Yes	T3,T7,T16	INPUT
otp_lc_data_i.state[319:0]	Yes	Yes	T3,T16,T85	Yes	T3,T16,T85	INPUT
otp_lc_data_i.error	Yes	Yes	T15,T7,T19	Yes	T15,T7,T19	INPUT
otp_lc_data_i.valid	Yes	Yes	T3,T16,T20	Yes	T3,T16,T20	INPUT
lc_dft_en_o[3:0]	Yes	Yes	T90,T92,T94	Yes	T87,T90,T92	OUTPUT
lc_nvm_debug_en_o[3:0]	Yes	Yes	T90,T92,T94	Yes	T87,T90,T92	OUTPUT
lc_hw_debug_en_o[3:0]	Yes	Yes	T90,T92,T94	Yes	T87,T90,T92	OUTPUT
lc_cpu_en_o[3:0]	Yes	Yes	T90,T92,T94	Yes	T60,T87,T90	OUTPUT
lc_creator_seed_sw_rw_en_o[3:0]	Yes	Yes	T92,T94,T99	Yes	T60,T92,T93	OUTPUT
lc_owner_seed_sw_rw_en_o[3:0]	Yes	Yes	T92,T94,T99	Yes	T60,T92,T93	OUTPUT
lc_iso_part_sw_rd_en_o[3:0]	Yes	Yes	T92,T94,T103	Yes	T60,T92,T94	OUTPUT
lc_iso_part_sw_wr_en_o[3:0]	Yes	Yes	T90,T92,T94	Yes	T60,T87,T90	OUTPUT
lc_seed_hw_rd_en_o[3:0]	Yes	Yes	T92,T105,T106	Yes	T92,T107,T108	OUTPUT
lc_keymgr_en_o[3:0]	Yes	Yes	T92,T94,T99	Yes	T60,T92,T93	OUTPUT
lc_escalate_en_o[3:0]	Yes	Yes	T109,T110,T106	Yes	T88,T109,T110	OUTPUT
lc_check_byp_en_o[3:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
lc_clk_byp_req_o[3:0]	Yes	Yes	T7,T43,T21	Yes	T1,T7,T32	OUTPUT
lc_clk_byp_ack_i[3:0]	Yes	Yes	T5,T15,T7	Yes	T5,T15,T7	INPUT
lc_flash_rma_seed_o[31:0]	Yes	Yes	T1,T4,T5	Yes	T111,T1,T4	OUTPUT
lc_flash_rma_req_o[3:0]	Yes	Yes	T5,T6,T13	Yes	T5,T6,T13	OUTPUT
lc_flash_rma_ack_i[3:0]	Yes	Yes	T5,T6,T13	Yes	T5,T6,T13	INPUT
lc_keymgr_div_o[127:0]	Yes	Yes	T92,T94,T103	Yes	T60,T92,T94	OUTPUT
otp_device_id_i[255:0]	Yes	Yes	T90,T100,T112	Yes	T90,T93,T113	INPUT
otp_manuf_state_i[255:0]	Yes	Yes	T90,T92,T103	Yes	T87,T90,T91	INPUT
hw_rev_o.reserved[23:0]	No	No		No		OUTPUT
hw_rev_o.revision_id[7:0]	No	No		No		OUTPUT
hw_rev_o.product_id[15:0]	No	No		No		OUTPUT
hw_rev_o.silicon_creator_id[15:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		31	31	100.00
IF	342	3	3	100.00
IF	376	3	3	100.00
IF	387	18	18	100.00
IF	462	3	3	100.00
IF	664	2	2	100.00
IF	521	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	342	if (prim_mubi_pkg::mubi8_test_true_strict(tap_claim_transition_if_q))
-2-:	351	if (prim_mubi_pkg::mubi8_test_true_strict(sw_claim_transition_if_q))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T6,T7
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	376	if ((prim_mubi_pkg::mubi8_test_false_loose(sw_claim_transition_if_q) && tap_reg2hw.claim_transition_if.qe))
-2-:	380	if ((prim_mubi_pkg::mubi8_test_false_loose(tap_claim_transition_if_q) && reg2hw.claim_transition_if.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T6,T7
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	387	if (lc_idle_d)
-2-:	389	if (prim_mubi_pkg::mubi8_test_true_strict(tap_claim_transition_if_q))
-3-:	393	if (tap_reg2hw.transition_ctrl.ext_clock_en.qe)
-4-:	402	if (tap_reg2hw.transition_ctrl.volatile_raw_unlock.qe)
-5-:	413	if (tap_reg2hw.transition_target.qe)
-6-:	420	if (tap_reg2hw.otp_vendor_test_ctrl.qe)
-7-:	423	if (prim_mubi_pkg::mubi8_test_true_strict(sw_claim_transition_if_q))
-8-:	427	if (reg2hw.transition_ctrl.ext_clock_en.qe)
-9-:	436	if (reg2hw.transition_ctrl.volatile_raw_unlock.qe)
-10-:	447	if (reg2hw.transition_target.qe)
-11-:	454	if (reg2hw.otp_vendor_test_ctrl.qe)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
1	1	1	-	-	-	-	-	-	-	-	Covered	T1,T22,T114
1	1	0	-	-	-	-	-	-	-	-	Covered	T1,T6,T7
1	1	-	1	-	-	-	-	-	-	-	Covered	T1,T22,T114
1	1	-	0	-	-	-	-	-	-	-	Covered	T1,T6,T7
1	1	-	-	1	-	-	-	-	-	-	Covered	T1,T6,T7
1	1	-	-	0	-	-	-	-	-	-	Covered	T1,T6,T7
1	1	-	-	-	1	-	-	-	-	-	Covered	T1,T6,T7
1	1	-	-	-	0	-	-	-	-	-	Covered	T1,T6,T7
1	0	-	-	-	-	1	1	-	-	-	Covered	T1,T7,T31
1	0	-	-	-	-	1	0	-	-	-	Covered	T1,T3,T4
1	0	-	-	-	-	1	-	1	-	-	Covered	T1,T7,T31
1	0	-	-	-	-	1	-	0	-	-	Covered	T1,T3,T4
1	0	-	-	-	-	1	-	-	1	-	Covered	T1,T4,T5
1	0	-	-	-	-	1	-	-	0	-	Covered	T1,T3,T4
1	0	-	-	-	-	1	-	-	-	1	Covered	T1,T4,T5
1	0	-	-	-	-	1	-	-	-	0	Covered	T1,T3,T4
1	0	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	462	if ((!rst_ni))
-2-:	487	if (((SecVolatileRawUnlockEn && transition_cmd) && (!volatile_raw_unlock_q)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T11
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	664	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	521	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	28	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	28	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	54237172	51208049	0	0
DecLcCountWidthCheck_A	797	797	0	0
DecLcIdStateWidthCheck_A	797	797	0	0
DecLcStateWidthCheck_A	797	797	0	0
FpvSecCmCtrlKmacIfFsmCheck_A	52918115	0	0	0
FpvSecCmCtrlLcCntCheck_A	50238239	1	0	0
FpvSecCmCtrlLcFsmCheck_A	52961868	0	0	0
FpvSecCmCtrlLcStateCheck_A	50928824	0	0	0
FpvSecCmRegWeOnehotCheck_A	54237172	80	0	0
FpvSecCmTapRegWeOnehotCheck_A	54237172	0	0	0
LcCheckBypassEnKnown_A	54237172	51208049	0	0
LcClkBypReqKnown_A	54237172	51208049	0	0
LcCpuEnKnown_A	54237172	51208049	0	0
LcCreatorSwRwEn_A	54237172	51208049	0	0
LcDftEnKnown_A	54237172	51208049	0	0
LcEscalateEnKnown_A	54237172	51208049	0	0
LcFlashRmaReqKnown_A	54237172	51208049	0	0
LcFlashRmaSeedKnown_A	54237172	51208049	0	0
LcHwDebugEnKnown_A	54237172	51208049	0	0
LcIsoSwRwEn_A	54237172	51208049	0	0
LcIsoSwWrEn_A	54237172	51208049	0	0
LcKeymgrDiv_A	54237172	51208049	0	0
LcKeymgrEnKnown_A	54237172	51208049	0	0
LcNvmDebugEnKnown_A	54237172	51208049	0	0
LcOtpProgramKnown_A	54237172	51208049	0	0
LcOtpTokenKnown_A	54237172	51208049	0	0
LcOwnerSwRwEn_A	54237172	51208049	0	0
LcSeedHwRdEn_A	54237172	51208049	0	0
NumTokenWordsCheck_A	797	797	0	0
OtpTestCtrlWidth_A	797	797	0	0
PwrLcKnown_A	54237172	51208049	0	0
TlOKnown	54237172	51208049	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

DecLcCountWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797	797	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

DecLcIdStateWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797	797	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

DecLcStateWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797	797	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

FpvSecCmCtrlKmacIfFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52918115	0	0	0

FpvSecCmCtrlLcCntCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50238239	1	0	0
T115	714897	1	0	0
T116	19354	0	0	0
T117	31180	0	0	0
T118	9370	0	0	0
T119	75767	0	0	0
T120	9165	0	0	0
T121	1007	0	0	0
T122	32566	0	0	0
T123	30395	0	0	0
T124	38540	0	0	0

FpvSecCmCtrlLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52961868	0	0	0

FpvSecCmCtrlLcStateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50928824	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	80	0	0
T62	35416	0	0	0
T66	20055	20	0	0
T95	0	20	0	0
T96	0	20	0	0
T125	0	10	0	0
T126	0	10	0	0
T127	28425	0	0	0
T128	375516	0	0	0
T129	36791	0	0	0
T130	1704	0	0	0
T131	9974	0	0	0
T132	34699	0	0	0
T133	87764	0	0	0
T134	76706	0	0	0

FpvSecCmTapRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	0	0	0

LcCheckBypassEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcClkBypReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcCpuEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcCreatorSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcDftEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcEscalateEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcFlashRmaReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcFlashRmaSeedKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcHwDebugEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcIsoSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcIsoSwWrEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcKeymgrDiv_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcKeymgrEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcNvmDebugEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcOtpProgramKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcOtpTokenKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcOwnerSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

LcSeedHwRdEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

NumTokenWordsCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797	797	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpTestCtrlWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797	797	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

PwrLcKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0

TlOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	54237172	51208049	0	0
T1	66323	66269	0	0
T2	2104	2009	0	0
T3	37730	30499	0	0
T4	21255	16331	0	0
T5	32857	28522	0	0
T6	30031	29182	0	0
T11	39306	35324	0	0
T12	7059	6347	0	0
T13	39798	32997	0	0
T14	33781	27759	0	0