Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.75	100.00	83.10	98.16		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	56338184	13773	0	0
claim_transition_if_regwen_rd_A	56338184	485	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56338184	13773	0	0
T89	3972	810	0	0
T90	13350	0	0	0
T91	5409	0	0	0
T92	4238	7	0	0
T93	15946	1074	0	0
T94	3780	87	0	0
T99	1428	15	0	0
T100	7868	0	0	0
T101	0	5	0	0
T103	0	18	0	0
T104	0	2	0	0
T107	1723	0	0	0
T113	32768	0	0	0
T138	0	705	0	0
T158	0	26	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56338184	485	0	0
T93	15946	12	0	0
T94	3780	0	0	0
T99	1428	0	0	0
T100	7868	0	0	0
T103	2036	3	0	0
T104	1339	0	0	0
T105	0	45	0	0
T107	1723	0	0	0
T108	0	5	0	0
T109	0	21	0	0
T112	1728	0	0	0
T113	32768	0	0	0
T139	0	7	0	0
T147	0	21	0	0
T152	3575	0	0	0
T158	0	5	0	0
T159	0	7	0	0
T160	0	10	0	0