Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.99	100.00	81.16	98.17		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	248853978	59938	0	0
claim_transition_if_regwen_rd_A	248853978	2833	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248853978	59938	0	0
T4	508588	1	0	0
T5	100520	0	0	0
T6	71439	0	0	0
T8	23548	0	0	0
T9	4732	0	0	0
T10	1547	0	0	0
T11	58216	0	0	0
T13	0	3	0	0
T14	4885	0	0	0
T15	20023	0	0	0
T20	20641	0	0	0
T37	0	9	0	0
T42	0	14	0	0
T95	0	2	0	0
T111	0	13	0	0
T165	0	1	0	0
T166	0	6	0	0
T167	0	7	0	0
T168	0	1	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248853978	2833	0	0
T110	0	1	0	0
T169	386110	7	0	0
T170	0	12	0	0
T171	0	12	0	0
T172	0	18	0	0
T173	0	4	0	0
T174	0	15	0	0
T175	0	15	0	0
T176	0	6	0	0
T177	0	3	0	0
T178	6867	0	0	0
T179	29120	0	0	0
T180	23759	0	0	0
T181	4455	0	0	0
T182	27135	0	0	0
T183	29594	0	0	0
T184	40248	0	0	0
T185	5253	0	0	0
T186	12698	0	0	0