Unified Coverage Report :: Module :: lc_ctrl

Module : lc_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.99	100.00	81.16	98.17		100.00	90.62

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	93.99	100.00	81.16	98.17		100.00	90.62

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.99	100.00	81.16	98.17		100.00	90.62

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.60	97.37	82.01	91.96	95.35	95.88	99.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_alert_tx[2].u_prim_alert_sender	100.00			100.00
lc_ctrl_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_dmi_jtag	95.65			95.65
u_lc_ctrl_fsm	95.64	99.06	88.46		97.30	95.69	97.67
u_lc_ctrl_kmac_if	95.42	98.21	100.00		83.33	95.56	100.00
u_prim_clock_mux2	85.19	100.00	55.56				100.00
u_prim_esc_receiver0	16.07			16.07
u_prim_esc_receiver1	16.07			16.07
u_prim_flop_2sync_init	100.00	100.00				100.00
u_prim_lc_sync	100.00	100.00					100.00
u_prim_mubi4_dec	0.00	0.00
u_prim_rst_n_mux2	85.19	100.00	55.56				100.00
u_reg	99.44	97.79	99.43	100.00		100.00	100.00
u_reg_tap	80.36	95.78	64.63	50.24		91.18	100.00
u_tap_tlul_host	70.98	96.08	61.90	6.90		90.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : lc_ctrl

	Line No.	Total	Covered	Percent
TOTAL		130	130	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
ALWAYS	315	41	41	100.00
ALWAYS	366	41	41	100.00
ALWAYS	464	32	32	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	565	1	1	100.00
CONT_ASSIGN	571	1	1	100.00
CONT_ASSIGN	580	1	1	100.00
ALWAYS	666	5	5	100.00
CONT_ASSIGN	675	1	1	100.00
CONT_ASSIGN	676	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
213	1	1
266	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
333	1	1
334	1	1
335	1	1
336	1	1
339	1	1
342	1	1
343	1	1
344	1	1
345	1	1
346	1	1
347	1	1
348	1	1
350	1	1
351	1	1
352	1	1
353	1	1
354	1	1
355	1	1
356	1	1
357	1	1
359	1	1
360	1	1
361	1	1
			MISSING_ELSE
366	1	1
367	1	1
368	1	1
369	1	1
370	1	1
371	1	1
372	1	1
373	1	1
378	1	1
380	1	1
382	1	1
384	1	1
			MISSING_ELSE
389	1	1
391	1	1
392	1	1
395	1	1
396	1	1
			MISSING_ELSE
404	1	1
405	1	1
			MISSING_ELSE
409	1	1
410	1	1
411	1	1
			MISSING_ELSE
415	1	1
416	1	1
417	1	1
			MISSING_ELSE
422	1	1
423	1	1
			MISSING_ELSE
425	1	1
426	1	1
429	1	1
430	1	1
			MISSING_ELSE
438	1	1
439	1	1
			MISSING_ELSE
443	1	1
444	1	1
445	1	1
			MISSING_ELSE
449	1	1
450	1	1
451	1	1
			MISSING_ELSE
456	1	1
457	1	1
			MISSING_ELSE
			MISSING_ELSE
			MISSING_ELSE
464	1	1
465	1	1
466	1	1
467	1	1
468	1	1
469	1	1
470	1	1
471	1	1
472	1	1
473	1	1
474	1	1
475	1	1
476	1	1
477	1	1
478	1	1
479	1	1
489	1	1
490		unreachable
492	1	1
495	1	1
496	1	1
497	1	1
498	1	1
499	1	1
500	1	1
501	1	1
502	1	1
506	1	1
507	1	1
508	1	1
509	1	1
510	1	1
511	1	1
531	1	1
536	1	1
552	1	1
554	1	1
565	1	1
571	1	1
580	1	1
666	1	1
667	1	1
668	1	1
670	1	1
671	1	1
675	1	1
676	1	1

---

Cond Coverage for Module : lc_ctrl

	Total	Covered	Percent
Conditions	69	56	81.16
Logical	69	56	81.16
Non-Logical	0	0
Event	0	0

 LINE       213
 EXPRESSION (dmi_req_ready & dmi_resp_ready)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       240
 EXPRESSION (dmi_req_valid & dmi_resp_ready)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       240
 EXPRESSION (dmi_req.op == DTM_WRITE)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       392
 EXPRESSION (tap_reg2hw.transition_cmd.q & tap_reg2hw.transition_cmd.qe)
             -------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T20

 LINE       426
 EXPRESSION (reg2hw.transition_cmd.q & reg2hw.transition_cmd.qe)
             -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T8
1	1	Covered	T3,T4,T8

 LINE       492
 EXPRESSION (trans_success_d | trans_success_q)
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T4,T8,T9

 LINE       495
 EXPRESSION (trans_cnt_oflw_error_d | trans_cnt_oflw_error_q)
             -----------1----------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T11
1	0	Covered	T4,T8,T11

 LINE       496
 EXPRESSION (trans_invalid_error_d | trans_invalid_error_q)
             ----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T11
1	0	Covered	T4,T8,T11

 LINE       497
 EXPRESSION (token_invalid_error_d | token_invalid_error_q)
             ----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T11
1	0	Covered	T4,T8,T11

 LINE       498
 EXPRESSION (flash_rma_error_d | flash_rma_error_q)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T11
1	0	Covered	T4,T8,T11

 LINE       499
 EXPRESSION (otp_prog_error_d | fatal_prog_error_q)
             --------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       500
 EXPRESSION (state_invalid_error_d | fatal_state_error_q)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T32,T34
1	0	Covered	T4,T32,T34

 LINE       501
 EXPRESSION (otp_lc_data_i.error | otp_part_error_q)
             ---------1---------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T22,T16
1	0	Covered	T4,T8,T11

 LINE       502
 EXPRESSION (fatal_bus_integ_error_csr_d | fatal_bus_integ_error_tap_d | fatal_bus_integ_error_q)
             -------------1-------------   -------------2-------------   -----------3-----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T51,T52,T53
1	0	0	Covered	T51,T52,T53

 LINE       571
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T84
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T10,T84

 LINE       571
 SUB-EXPRESSION (reg2hw.alert_test.fatal_state_error.q & reg2hw.alert_test.fatal_state_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T84
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T10,T84

 LINE       571
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prog_error.q & reg2hw.alert_test.fatal_prog_error.qe)
                 ------------------1-----------------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T84
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T10,T84

 LINE       580
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_bus_integ_error.q & tap_reg2hw.alert_test.fatal_bus_integ_error.qe)
                 ----------------------1----------------------   -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Not Covered

 LINE       580
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_state_error.q & tap_reg2hw.alert_test.fatal_state_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Not Covered

 LINE       580
 SUB-EXPRESSION (tap_reg2hw.alert_test.fatal_prog_error.q & tap_reg2hw.alert_test.fatal_prog_error.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Not Covered

 LINE       593
 EXPRESSION (alert_test[0] | tap_alert_test[0])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T10,T84

 LINE       593
 EXPRESSION (alert_test[1] | tap_alert_test[1])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T10,T84

 LINE       593
 EXPRESSION (alert_test[2] | tap_alert_test[2])
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T10,T84

---

Toggle Coverage for Module : lc_ctrl

	Total	Covered	Percent
Totals	104	99	95.19
Total Bits	7424	7288	98.17
Total Bits 0->1	3712	3644	98.17
Total Bits 1->0	3712	3644	98.17

Ports	104	99	95.19
Port Bits	7424	7288	98.17
Port Bits 0->1	3712	3644	98.17
Port Bits 1->0	3712	3644	98.17

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
clk_kmac_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_kmac_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T4,T10	Yes	T2,T4,T10	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_o.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_error	Yes	Yes	T4,T13,T37	Yes	T4,T13,T37	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T8	Yes	T3,T4,T8	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T4,T8	Yes	T2,T3,T4	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T3,T4,T8	Yes	T2,T3,T4	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T4,*T8	Yes	T3,T4,T8	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
jtag_i.tdi	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
jtag_i.trst_n	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
jtag_i.tms	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
jtag_i.tck	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
jtag_o.tdo_oe	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
jtag_o.tdo	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
scan_rst_ni	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
scanmode_i[3:0]	No	No		No		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T4,T10	Yes	T2,T4,T10	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T2,T10,T51	Yes	T2,T10,T51	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T4,T10	Yes	T2,T4,T10	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T2,T10,T51	Yes	T2,T10,T51	OUTPUT
esc_scrap_state0_tx_i.resp_n	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
esc_scrap_state0_tx_i.resp_p	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
esc_scrap_state0_rx_o.esc_n	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
esc_scrap_state0_rx_o.esc_p	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
esc_scrap_state1_tx_i.resp_n	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
esc_scrap_state1_tx_i.resp_p	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
esc_scrap_state1_rx_o.esc_n	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
esc_scrap_state1_rx_o.esc_p	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
pwr_lc_i.lc_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_lc_o.lc_idle	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
pwr_lc_o.lc_done	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
strap_en_override_o	Unreachable	Unreachable		Unreachable		OUTPUT
lc_otp_vendor_test_o.ctrl[31:0]	Yes	Yes	T1,T8,T5	Yes	T1,T8,T5	OUTPUT
lc_otp_vendor_test_i.status[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
lc_otp_program_o.count[383:0]	Yes	Yes	T4,T8,T32	Yes	T4,T8,T32	OUTPUT
lc_otp_program_o.state[319:0]	Yes	Yes	T4,T82,T59	Yes	T4,T82,T59	OUTPUT
lc_otp_program_o.req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
lc_otp_program_i.ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
lc_otp_program_i.err	Yes	Yes	T4,T59,T13	Yes	T4,T59,T13	INPUT
kmac_data_i.error	Yes	Yes	T4,T8,T11	Yes	T4,T8,T11	INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	INPUT
kmac_data_i.done	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	OUTPUT
kmac_data_o.strb[7:0]	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	OUTPUT
kmac_data_o.data[63:0]	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	OUTPUT
kmac_data_o.valid	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	OUTPUT
otp_lc_data_i.rma_token[127:0]	Yes	Yes	T1,T3,T4	Yes	T3,T4,T8	INPUT
otp_lc_data_i.rma_token_valid[3:0]	Yes	Yes	T57,T58,T36	Yes	T57,T58,T36	INPUT
otp_lc_data_i.test_exit_token[127:0]	Yes	Yes	T1,T3,T4	Yes	T3,T4,T8	INPUT
otp_lc_data_i.test_unlock_token[127:0]	Yes	Yes	T3,T4,T8	Yes	T3,T4,T8	INPUT
otp_lc_data_i.test_tokens_valid[3:0]	Yes	Yes	T57,T58,T36	Yes	T57,T58,T36	INPUT
otp_lc_data_i.secrets_valid[3:0]	Yes	Yes	T57,T58,T36	Yes	T57,T58,T36	INPUT
otp_lc_data_i.count[383:0]	Yes	Yes	T4,T8,T32	Yes	T4,T8,T32	INPUT
otp_lc_data_i.state[319:0]	Yes	Yes	T4,T82,T59	Yes	T4,T82,T59	INPUT
otp_lc_data_i.error	Yes	Yes	T4,T8,T11	Yes	T4,T8,T11	INPUT
otp_lc_data_i.valid	Yes	Yes	T4,T32,T34	Yes	T4,T32,T34	INPUT
lc_dft_en_o[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
lc_nvm_debug_en_o[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
lc_hw_debug_en_o[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
lc_cpu_en_o[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
lc_creator_seed_sw_rw_en_o[3:0]	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	OUTPUT
lc_owner_seed_sw_rw_en_o[3:0]	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	OUTPUT
lc_iso_part_sw_rd_en_o[3:0]	Yes	Yes	T4,T8,T11	Yes	T4,T8,T11	OUTPUT
lc_iso_part_sw_wr_en_o[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
lc_seed_hw_rd_en_o[3:0]	Yes	Yes	T4,T8,T11	Yes	T4,T8,T11	OUTPUT
lc_keymgr_en_o[3:0]	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	OUTPUT
lc_escalate_en_o[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
lc_check_byp_en_o[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
lc_clk_byp_req_o[3:0]	Yes	Yes	T4,T9,T20	Yes	T4,T9,T5	OUTPUT
lc_clk_byp_ack_i[3:0]	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	INPUT
lc_flash_rma_seed_o[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
lc_flash_rma_req_o[3:0]	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	OUTPUT
lc_keymgr_div_o[127:0]	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	OUTPUT
otp_device_id_i[255:0]	Yes	Yes	T4,T11,T14	Yes	T2,T4,T11	INPUT
otp_manuf_state_i[255:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
hw_rev_o.reserved[23:0]	No	No		No		OUTPUT
hw_rev_o.revision_id[7:0]	No	No		No		OUTPUT
hw_rev_o.product_id[15:0]	No	No		No		OUTPUT
hw_rev_o.silicon_creator_id[15:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : lc_ctrl

	Line No.	Total	Covered	Percent
Branches		28	28	100.00
IF	344	3	3	100.00
IF	378	3	3	100.00
IF	389	18	18	100.00
IF	464	2	2	100.00
IF	666	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	344	if (prim_mubi_pkg::mubi8_test_true_strict(tap_claim_transition_if_q))
-2-:	353	if (prim_mubi_pkg::mubi8_test_true_strict(sw_claim_transition_if_q))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T3,T4,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	378	if ((prim_mubi_pkg::mubi8_test_false_loose(sw_claim_transition_if_q) && tap_reg2hw.claim_transition_if.qe))
-2-:	382	if ((prim_mubi_pkg::mubi8_test_false_loose(tap_claim_transition_if_q) && reg2hw.claim_transition_if.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T3,T4,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	389	if (lc_idle_d)
-2-:	391	if (prim_mubi_pkg::mubi8_test_true_strict(tap_claim_transition_if_q))
-3-:	395	if (tap_reg2hw.transition_ctrl.ext_clock_en.qe)
-4-:	404	if (tap_reg2hw.transition_ctrl.volatile_raw_unlock.qe)
-5-:	415	if (tap_reg2hw.transition_target.qe)
-6-:	422	if (tap_reg2hw.otp_vendor_test_ctrl.qe)
-7-:	425	if (prim_mubi_pkg::mubi8_test_true_strict(sw_claim_transition_if_q))
-8-:	429	if (reg2hw.transition_ctrl.ext_clock_en.qe)
-9-:	438	if (reg2hw.transition_ctrl.volatile_raw_unlock.qe)
-10-:	449	if (reg2hw.transition_target.qe)
-11-:	456	if (reg2hw.otp_vendor_test_ctrl.qe)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
1	1	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
1	1	0	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
1	1	-	1	-	-	-	-	-	-	-	Covered	T4,T5,T6
1	1	-	0	-	-	-	-	-	-	-	Covered	T1,T4,T5
1	1	-	-	1	-	-	-	-	-	-	Covered	T1,T4,T5
1	1	-	-	0	-	-	-	-	-	-	Covered	T1,T4,T5
1	1	-	-	-	1	-	-	-	-	-	Covered	T1,T4,T5
1	1	-	-	-	0	-	-	-	-	-	Covered	T1,T4,T5
1	0	-	-	-	-	1	1	-	-	-	Covered	T4,T9,T5
1	0	-	-	-	-	1	0	-	-	-	Covered	T3,T4,T8
1	0	-	-	-	-	1	-	1	-	-	Covered	T4,T9,T5
1	0	-	-	-	-	1	-	0	-	-	Covered	T3,T4,T8
1	0	-	-	-	-	1	-	-	1	-	Covered	T3,T4,T8
1	0	-	-	-	-	1	-	-	0	-	Covered	T3,T4,T8
1	0	-	-	-	-	1	-	-	-	1	Covered	T3,T4,T8
1	0	-	-	-	-	1	-	-	-	0	Covered	T3,T4,T8
1	0	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	489	if (((SecVolatileRawUnlockEn && transition_cmd) && (!volatile_raw_unlock_q)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Unreachable
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	666	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : lc_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	29	90.62
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	29	90.62

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	244210716	235143120	0	0
DecLcCountWidthCheck_A	1617	1617	0	0
DecLcIdStateWidthCheck_A	1617	1617	0	0
DecLcStateWidthCheck_A	1617	1617	0	0
FpvSecCmCtrlKmacIfFsmCheck_A	238356548	0	0	0
FpvSecCmCtrlLcCntCheck_A	225981828	1	0	0
FpvSecCmCtrlLcFsmCheck_A	238511792	0	0	0
FpvSecCmCtrlLcStateCheck_A	231649591	3	0	0
FpvSecCmRegWeOnehotCheck_A	244210716	170	0	0
FpvSecCmTapRegWeOnehotCheck_A	244210716	0	0	0
LcCheckBypassEnKnown_A	244210716	235143120	0	0
LcClkBypReqKnown_A	244210716	235143120	0	0
LcCpuEnKnown_A	244210716	235143120	0	0
LcCreatorSwRwEn_A	244210716	235143120	0	0
LcDftEnKnown_A	244210716	235143120	0	0
LcEscalateEnKnown_A	244210716	235143120	0	0
LcFlashRmaReqKnown_A	244210716	235143120	0	0
LcFlashRmaSeedKnown_A	244210716	235143120	0	0
LcHwDebugEnKnown_A	244210716	235143120	0	0
LcIsoSwRwEn_A	244210716	235143120	0	0
LcIsoSwWrEn_A	244210716	235143120	0	0
LcKeymgrDiv_A	244210716	235143120	0	0
LcKeymgrEnKnown_A	244210716	235143120	0	0
LcNvmDebugEnKnown_A	244210716	235143120	0	0
LcOtpProgramKnown_A	244210716	235143120	0	0
LcOtpTokenKnown_A	244210716	235143120	0	0
LcOwnerSwRwEn_A	244210716	235143120	0	0
LcSeedHwRdEn_A	244210716	235143120	0	0
NumTokenWordsCheck_A	1617	1617	0	0
OtpTestCtrlWidth_A	1617	1617	0	0
PwrLcKnown_A	244210716	235143120	0	0
TlOKnown	244210716	235143120	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

DecLcCountWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617	1617	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

DecLcIdStateWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617	1617	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

DecLcStateWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617	1617	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

FpvSecCmCtrlKmacIfFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238356548	0	0	0

FpvSecCmCtrlLcCntCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225981828	1	0	0
T85	271893	1	0	0
T86	367336	0	0	0
T87	46622	0	0	0
T88	1043	0	0	0
T89	798381	0	0	0
T90	1889	0	0	0
T91	31340	0	0	0
T92	33616	0	0	0
T93	21828	0	0	0
T94	267313	0	0	0

FpvSecCmCtrlLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238511792	0	0	0

FpvSecCmCtrlLcStateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231649591	3	0	0
T4	501203	1	0	0
T5	100520	0	0	0
T6	71439	0	0	0
T8	23548	0	0	0
T9	4732	0	0	0
T10	1547	0	0	0
T11	58216	0	0	0
T14	4885	0	0	0
T15	20023	0	0	0
T20	20641	0	0	0
T85	0	1	0	0
T95	0	1	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	170	0	0
T13	211594	0	0	0
T37	474989	0	0	0
T51	23389	20	0	0
T52	0	20	0	0
T53	0	20	0	0
T84	2107	0	0	0
T96	0	20	0	0
T97	0	20	0	0
T98	0	10	0	0
T99	0	10	0	0
T100	0	10	0	0
T101	0	20	0	0
T102	0	20	0	0
T103	29295	0	0	0
T104	86122	0	0	0
T105	42165	0	0	0
T106	17586	0	0	0
T107	987	0	0	0
T108	42661	0	0	0

FpvSecCmTapRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	0	0	0

LcCheckBypassEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcClkBypReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcCpuEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcCreatorSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcDftEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcEscalateEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcFlashRmaReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcFlashRmaSeedKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcHwDebugEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcIsoSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcIsoSwWrEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcKeymgrDiv_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcKeymgrEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcNvmDebugEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcOtpProgramKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcOtpTokenKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcOwnerSwRwEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcSeedHwRdEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

NumTokenWordsCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617	1617	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpTestCtrlWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617	1617	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

PwrLcKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

TlOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0