Unified Coverage Report :: Module :: lc_ctrl_fsm

Module : lc_ctrl_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.03	98.17	93.06		73.47	97.10	93.33

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_fsm	95.79	98.17	93.06		97.30	97.10	93.33

---

Module Instance : tb.dut.u_lc_ctrl_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.79	98.17	93.06		97.30	97.10	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.64	99.06	88.46		97.30	95.69	97.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.99	100.00	81.16	98.17		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_syncs[0].u_prim_lc_sync_flash_rma_ack	100.00	100.00				100.00	100.00
gen_syncs[1].u_prim_lc_sync_flash_rma_ack	100.00	100.00				100.00	100.00
u_cnt_regs	100.00	100.00				100.00	100.00
u_fsm_state_regs	100.00	100.00				100.00	100.00
u_lc_ctrl_fsm_cov_if	96.97	100.00	90.91			100.00
u_lc_ctrl_signal_decode	98.86	99.21				97.37	100.00
u_lc_ctrl_state_decode	98.89	100.00	100.00			96.67
u_lc_ctrl_state_transition	81.26	96.97	57.14			89.66
u_prim_lc_sender_check_byp_en	100.00	100.00				100.00
u_prim_lc_sender_clk_byp_req	100.00	100.00				100.00
u_prim_lc_sender_flash_rma_req	100.00	100.00				100.00
u_prim_lc_sync_clk_byp_ack	100.00	100.00				100.00	100.00
u_prim_lc_sync_flash_rma_ack_buf	100.00	100.00					100.00
u_prim_lc_sync_rma_token_valid	100.00	100.00					100.00
u_prim_lc_sync_test_token_valid	100.00	100.00					100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : lc_ctrl_fsm

	Line No.	Total	Covered	Percent
TOTAL		164	161	98.17
CONT_ASSIGN	126	1	1	100.00
ALWAYS	146	3	3	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	204	104	102	98.08
ALWAYS	584	3	3	100.00
ALWAYS	585	3	3	100.00
ALWAYS	586	3	3	100.00
ALWAYS	589	3	3	100.00
CONT_ASSIGN	623	1	0	0.00
CONT_ASSIGN	666	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
ALWAYS	677	15	15	100.00
ALWAYS	712	14	14	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	740	1	1	100.00
CONT_ASSIGN	742	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
ALWAYS	882	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
126	1	1
146	1	1
147	1	1
148	1	1
171	1	1
178	1	1
179	1	1
204	1	1
205	1	1
206	1	1
209	1	1
210	1	1
213	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
231	1	1
232	1	1
238	1	1
239	1	1
240	1	1
242	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
254	1	1
255	1	1
			MISSING_ELSE
263	1	1
273	1	1
277	1	1
278	1	1
			==> MISSING_ELSE
284	1	1
285	1	1
293	1	1
295		unreachable
299		unreachable
301		unreachable
305		unreachable
309		unreachable
312		unreachable
314		unreachable
316		unreachable
317		unreachable
321		unreachable
326	1	1
327	1	1
			MISSING_ELSE
333	1	1
350	1	1
351	1	1
			MISSING_ELSE
			MISSING_ELSE
364	1	1
365	1	1
382	1	1
383	1	1
384	1	1
385	1	1
			MISSING_ELSE
388	1	1
391	1	1
398	1	1
399	1	1
401	1	1
407	1	1
411	1	1
412	1	1
413	1	1
			MISSING_ELSE
418	1	1
419	1	1
420	1	1
421	1	1
423	1	1
			MISSING_ELSE
431	1	1
432	1	1
434	1	1
445	1	1
446	1	1
452	1	1
455	1	1
457	1	1
458	1	1
			MISSING_ELSE
466	1	1
467	1	1
468	1	1
469	1	1
			MISSING_ELSE
472	1	1
482	1	1
483	1	1
487	1	1
493	1	1
496	1	1
499	1	1
501	1	1
504	0	1
505	0	1
509	1	1
510	1	1
520	1	1
524	1	1
525	1	1
526	1	1
529	1	1
533	1	1
534	1	1
535	1	1
536	1	1
537	1	1
538	1	1
			MISSING_ELSE
544	1	1
549	1	1
554	1	1
555	1	1
567	1	1
568	1	1
574	1	1
575	1	1
576	1	1
			MISSING_ELSE
584	3	3
585	3	3
586	3	3
589	1	1
590	1	1
592	1	1
623	0	1
666	1	1
667	1	1
668	1	1
677	1	1
679	1	1
681	1	1
684	1	1
685	1	1
			MISSING_ELSE
687	1	1
688	1	1
			MISSING_ELSE
691	1	1
692	1	1
			MISSING_ELSE
694	1	1
695	1	1
			MISSING_ELSE
698	1	1
699	1	1
			MISSING_ELSE
701	1	1
702	1	1
			MISSING_ELSE
712	1	1
713	1	1
714	1	1
715	1	1
716	1	1
717	1	1
718	1	1
720	1	1
721	1	1
722	1	1
723	1	1
724	1	1
725	1	1
726	1	1
732	1	1
736	1	1
740	1	1
742	1	1
749	1	1
882	3	3

---

Cond Coverage for Module : lc_ctrl_fsm

	Total	Covered	Percent
Conditions	72	67	93.06
Logical	72	67	93.06
Non-Logical	0	0
Event	0	0

 LINE       251
 EXPRESSION (init_req_i && lc_state_valid_q)
             -----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T32,T34
1	1	Covered	T1,T2,T3

 LINE       284
 EXPRESSION (lc_state_q == LcStScrap)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T20,T17

 LINE       295
 EXPRESSION ((lc_state_q == LcStRaw) && (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}) && ((!trans_invalid_error_o)))
             -----------1-----------    ----------------------------------------2---------------------------------------    -------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       295
 SUB-EXPRESSION (lc_state_q == LcStRaw)
                -----------1-----------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       295
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})
                ----------------------------------------1---------------------------------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       299
 EXPRESSION (unhashed_token_i == lc_ctrl_state_pkg::RndCnstRawUnlockTokenHashed)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       305
 EXPRESSION ((lc_cnt_q == LcCnt0) ? LcCnt1 : lc_cnt_q)
             ----------1---------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       305
 SUB-EXPRESSION (lc_cnt_q == LcCnt0)
                ----------1---------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       411
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[1])
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T4,T8,T11

 LINE       452
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T8,T11
1	0	1	Covered	T4,T8,T11
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T9

 LINE       452
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T4,T8,T11
1	Covered	T4,T8,T9

 LINE       466
 EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T4,T8,T9

 LINE       493
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T9

 LINE       493
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T8,T9

 LINE       496
 EXPRESSION (fsm_state_q == TokenCheck1St)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T4,T8,T9

 LINE       524
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[2])
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T4,T12,T35

 LINE       529
 EXPRESSION 
 Number  Term
      1  ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off))) || 
      2  ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T9
0	1	Covered	T4,T16,T36
1	0	Covered	T13,T37,T35

 LINE       529
 SUB-EXPRESSION ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off)))
                 -----------------------------------1----------------------------------    --------------------------------2--------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T20
1	0	Covered	T4,T8,T9
1	1	Covered	T13,T37,T35

 LINE       529
 SUB-EXPRESSION (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T4,T9,T20
1	Covered	T4,T8,T9

 LINE       529
 SUB-EXPRESSION ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off))
                 -------------1-------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T9
0	1	Covered	T13,T37,T35
1	0	Covered	T38,T39,T40

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_req_o != Off)
                -------------1-------------

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T4,T9,T20

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_ack_buf[2] != Off)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T4,T9,T20

 LINE       529
 SUB-EXPRESSION ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On)))
                 -----------------------------------1----------------------------------    -------------------------------2-------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Covered	T4,T9,T20
1	1	Covered	T4,T16,T36

 LINE       529
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T4,T9,T20

 LINE       529
 SUB-EXPRESSION ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On))
                 -------------1------------    ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T20
0	1	Covered	T4,T16,T36
1	0	Covered	T41,T42,T43

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_req_o != On)
                -------------1------------

-1-	Status	Tests
0	Covered	T4,T9,T20
1	Covered	T4,T8,T9

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_ack_buf[2] != On)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T9,T20
1	Covered	T4,T8,T9

 LINE       567
 EXPRESSION (esc_scrap_state0_i || esc_scrap_state1_i)
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       574
 EXPRESSION ((((|state_invalid_error)) | token_if_fsm_err_i) && (fsm_state_q != EscalateSt))
             -----------------------1-----------------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T32,T34
1	1	Covered	T4,T32,T34

 LINE       574
 SUB-EXPRESSION (((|state_invalid_error)) | token_if_fsm_err_i)
                 ------------1-----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T32,T34
1	0	Covered	T4,T32,T34

 LINE       574
 SUB-EXPRESSION (fsm_state_q != EscalateSt)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       732
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[0]][trans_target_i[0]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       732
 SUB-EXPRESSION ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Unreachable	T5,T6,T7
1	1	Covered	T1,T2,T3

 LINE       736
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[1]][trans_target_i[1]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       736
 SUB-EXPRESSION ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Unreachable	T5,T6,T44
1	1	Covered	T1,T2,T3

 LINE       749
 EXPRESSION (trans_invalid_error || (token_idx0 != token_idx1))
             ---------1---------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T19
1	0	Covered	T4,T8,T11

 LINE       749
 SUB-EXPRESSION (token_idx0 != token_idx1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T19

---

FSM Coverage for Module : lc_ctrl_fsm

Summary for FSM :: fsm_state_q

	Total	Covered	Percent
States	15	15	100.00	(Not included in score)
Transitions	47	34	72.34
Sequences	0	0

State, Transition and Sequence Details for FSM :: fsm_state_q

---

states	Line No.	Covered	Tests
ClkMuxSt	327	Covered	T1,T3,T4
CntIncrSt	385	Covered	T1,T3,T4
CntProgSt	401	Covered	T1,T3,T4
EscalateSt	568	Covered	T1,T3,T4
FlashRmaSt	455	Covered	T4,T8,T9
IdleSt	252	Covered	T1,T2,T3
InvalidSt	575	Covered	T4,T32,T34
PostTransSt	317	Covered	T1,T3,T4
ResetSt	246	Covered	T1,T2,T3
ScrapSt	285	Covered	T4,T20,T17
TokenCheck0St	469	Covered	T4,T8,T9
TokenCheck1St	501	Covered	T4,T8,T9
TokenHashSt	434	Covered	T4,T8,T9
TransCheckSt	423	Covered	T4,T8,T9
TransProgSt	499	Covered	T4,T8,T9

transitions	Line No.	Covered	Tests
ClkMuxSt->CntIncrSt	385	Covered	T1,T3,T4
ClkMuxSt->EscalateSt	568	Covered	T17,T45,T46
ClkMuxSt->InvalidSt	575	Not Covered
CntIncrSt->CntProgSt	401	Covered	T1,T3,T4
CntIncrSt->EscalateSt	568	Covered	T17,T45,T46
CntIncrSt->InvalidSt	575	Not Covered
CntIncrSt->PostTransSt	399	Covered	T4,T8,T11
CntProgSt->EscalateSt	568	Covered	T17,T45,T46
CntProgSt->InvalidSt	575	Not Covered
CntProgSt->PostTransSt	412	Covered	T1,T3,T4
CntProgSt->TransCheckSt	423	Covered	T4,T8,T9
EscalateSt->InvalidSt	575	Not Covered
FlashRmaSt->EscalateSt	568	Covered	T17,T46,T47
FlashRmaSt->InvalidSt	575	Not Covered
FlashRmaSt->TokenCheck0St	469	Covered	T4,T8,T9
IdleSt->ClkMuxSt	327	Covered	T1,T3,T4
IdleSt->EscalateSt	568	Covered	T48,T49,T50
IdleSt->InvalidSt	575	Covered	T4,T32,T34
IdleSt->PostTransSt	317	Not Covered
IdleSt->ScrapSt	285	Covered	T4,T20,T17
InvalidSt->EscalateSt	568	Covered	T4,T32,T34
PostTransSt->EscalateSt	568	Covered	T1,T3,T4
PostTransSt->InvalidSt	575	Not Covered
ResetSt->EscalateSt	568	Covered	T17,T45,T46
ResetSt->IdleSt	252	Covered	T1,T2,T3
ResetSt->InvalidSt	575	Not Covered
ScrapSt->EscalateSt	568	Covered	T17,T45,T46
ScrapSt->InvalidSt	575	Covered	T51,T52,T53
TokenCheck0St->EscalateSt	568	Covered	T17,T45,T48
TokenCheck0St->InvalidSt	575	Not Covered
TokenCheck0St->PostTransSt	483	Covered	T4,T8,T11
TokenCheck0St->TokenCheck1St	501	Covered	T4,T8,T9
TokenCheck1St->EscalateSt	568	Covered	T17,T45,T46
TokenCheck1St->InvalidSt	575	Not Covered
TokenCheck1St->PostTransSt	483	Covered	T4,T11,T19
TokenCheck1St->TransProgSt	499	Covered	T4,T8,T9
TokenHashSt->EscalateSt	568	Covered	T4,T17,T45
TokenHashSt->FlashRmaSt	455	Covered	T4,T8,T9
TokenHashSt->InvalidSt	575	Not Covered
TokenHashSt->PostTransSt	457	Covered	T4,T8,T11
TransCheckSt->EscalateSt	568	Covered	T17,T45,T47
TransCheckSt->InvalidSt	575	Not Covered
TransCheckSt->PostTransSt	432	Covered	T4,T8,T11
TransCheckSt->TokenHashSt	434	Covered	T4,T8,T9
TransProgSt->EscalateSt	568	Covered	T17,T45,T46
TransProgSt->InvalidSt	575	Not Covered
TransProgSt->PostTransSt	525	Covered	T4,T8,T9

Summary for FSM :: lc_state_q

	Total	Covered	Percent
States	21	12	57.14	(Not included in score)
Transitions	1	1	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_state_q

---

states	Line No.	Covered	Tests
LcStDev	92	Not Covered
LcStProd	93	Not Covered
LcStProdEnd	94	Not Covered
LcStRaw	295	Covered	T2,T4,T8
LcStRma	333	Not Covered
LcStScrap	284	Not Covered
LcStTestLocked0	333	Covered	T4,T8,T9
LcStTestLocked1	333	Covered	T4,T8,T11
LcStTestLocked2	333	Covered	T1,T3,T4
LcStTestLocked3	333	Covered	T4,T8,T9
LcStTestLocked4	333	Covered	T4,T8,T9
LcStTestLocked5	333	Not Covered
LcStTestLocked6	333	Not Covered
LcStTestUnlocked0	301	Covered	T4,T8,T9
LcStTestUnlocked1	333	Covered	T3,T4,T8
LcStTestUnlocked2	333	Covered	T3,T4,T9
LcStTestUnlocked3	333	Covered	T3,T4,T8
LcStTestUnlocked4	333	Covered	T4,T8,T9
LcStTestUnlocked5	333	Covered	T1,T3,T4
LcStTestUnlocked6	333	Not Covered
LcStTestUnlocked7	333	Not Covered

transitions	Line No.	Covered	Tests
LcStRaw->LcStTestUnlocked0	301	Covered	T4,T8,T17

Summary for FSM :: lc_cnt_q

	Total	Covered	Percent
States	25	6	24.00	(Not included in score)
Transitions	1	1	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_cnt_q

---

states	Line No.	Covered	Tests
LcCnt0	305	Covered	T4,T8,T12
LcCnt1	305	Covered	T4,T8,T11
LcCnt10	112	Not Covered
LcCnt11	113	Not Covered
LcCnt12	114	Not Covered
LcCnt13	115	Not Covered
LcCnt14	116	Not Covered
LcCnt15	117	Not Covered
LcCnt16	118	Not Covered
LcCnt17	119	Not Covered
LcCnt18	120	Not Covered
LcCnt19	121	Not Covered
LcCnt2	104	Covered	T4,T8,T11
LcCnt20	122	Not Covered
LcCnt21	123	Not Covered
LcCnt22	124	Not Covered
LcCnt23	125	Not Covered
LcCnt24	126	Not Covered
LcCnt3	105	Covered	T2,T4,T8
LcCnt4	106	Covered	T4,T8,T9
LcCnt5	107	Covered	T4,T8,T9
LcCnt6	108	Not Covered
LcCnt7	109	Not Covered
LcCnt8	110	Not Covered
LcCnt9	111	Not Covered

transitions	Line No.	Covered	Tests
LcCnt0->LcCnt1	305	Covered	T8,T12,T37

---

Branch Coverage for Module : lc_ctrl_fsm

	Line No.	Total	Covered	Percent
Branches		69	67	97.10
TERNARY	732	1	1	100.00
TERNARY	736	1	1	100.00
CASE	242	42	40	95.24
IF	567	3	3	100.00
IF	584	2	2	100.00
IF	585	2	2	100.00
IF	586	2	2	100.00
IF	589	2	2	100.00
IF	684	2	2	100.00
IF	687	2	2	100.00
IF	691	2	2	100.00
IF	694	2	2	100.00
IF	698	2	2	100.00
IF	701	2	2	100.00
IF	882	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	732	(((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

	LineNo.	Expression
-1-:	736	(((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

	LineNo.	Expression
-1-:	242	case (fsm_state_q)
-2-:	251	if ((init_req_i && lc_state_valid_q))
-3-:	273	if (((!((SecVolatileRawUnlockEn && (lc_state_q == LcStTestUnlocked0)) && (lc_cnt_q != LcCnt0))) || prim_mubi_pkg::mubi8_test_false_loose(volatile_raw_unlock_success_q)))
-4-:	284	if ((lc_state_q == LcStScrap))
-5-:	293	if (((SecVolatileRawUnlockEn && volatile_raw_unlock_i) && trans_cmd_i))
-6-:	295	if ((((lc_state_q == LcStRaw) && (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})) && (!trans_invalid_error_o)))
-7-:	299	if ((unhashed_token_i == lc_ctrl_state_pkg::RndCnstRawUnlockTokenHashed))
-8-:	305	((lc_cnt_q == LcCnt0)) ? 
-9-:	326	if (trans_cmd_i)
-10-:	333	if ((lc_state_q inside {LcStRaw, LcStTestLocked0, LcStTestLocked1, LcStTestLocked2, LcStTestLocked3, LcStTestLocked4, LcStTestLocked5, LcStTestLocked6, LcStTestUnlocked0, LcStTestUnlocked1, LcStTestUnlocked2, LcStTestUnlocked3, LcStTestUnlocked4, LcStTestUnlocked5, LcStTestUnlocked6, LcStTestUnlocked7, LcStRma}))
-11-:	350	if (use_ext_clock_i)
-12-:	365	if ((lc_state_q inside {LcStRaw, LcStTestLocked0, LcStTestLocked1, LcStTestLocked2, LcStTestLocked3, LcStTestLocked4, LcStTestLocked5, LcStTestLocked6, LcStTestUnlocked0, LcStTestUnlocked1, LcStTestUnlocked2, LcStTestUnlocked3, LcStTestUnlocked4, LcStTestUnlocked5, LcStTestUnlocked6, LcStTestUnlocked7, LcStRma}))
-13-:	382	if (use_ext_clock_i)
-14-:	384	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_clk_byp_ack[0]))
-15-:	398	if (trans_cnt_oflw_error_o)
-16-:	411	if ((lc_clk_byp_req_o != lc_clk_byp_ack[1]))
-17-:	418	if (otp_prog_ack_i)
-18-:	419	if (otp_prog_err_i)
-19-:	431	if (trans_invalid_error_o)
-20-:	446	if (token_hash_ack_i)
-21-:	452	if ((((hashed_token_i == hashed_token_mux) && (!token_hash_err_i)) && (&hashed_token_valid_mux)))
-22-:	466	if ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}))
-23-:	468	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_ack_buf[0]))
-24-:	482	if (trans_invalid_error_o)
-25-:	487	if (((((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_flash_rma_req_o)) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_flash_rma_ack_buf[1])) || (((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_req_o)) && lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_ack_buf[1]))))
-26-:	493	if ((((hashed_token_i == hashed_token_mux) && (!token_hash_err_i)) && (&hashed_token_valid_mux)))
-27-:	496	if ((fsm_state_q == TokenCheck1St))
-28-:	524	if ((lc_clk_byp_req_o != lc_clk_byp_ack[2]))
-29-:	529	if ((((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off))) || ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On)))))
-30-:	535	if (otp_prog_ack_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T17
IdleSt	-	-	0	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IdleSt	-	-	0	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IdleSt	-	-	0	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IdleSt	-	-	0	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IdleSt	-	-	0	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	0	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T5
IdleSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T20
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T54,T37
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T11
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T11
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T11
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T11
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	Covered	T4,T8,T9
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	Covered	T4,T8,T9
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T19,T55,T56
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	1	-	-	-	Covered	T4,T8,T9
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	0	-	-	-	Covered	T4,T8,T9
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	-	-	-	-	Not Covered
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T8,T11
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T12,T35
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T16,T13
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	1	Covered	T4,T8,T9
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	Covered	T4,T8,T9
ScrapSt PostTransSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
EscalateSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
InvalidSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T32,T34
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T32,T34

	LineNo.	Expression
-1-:	567	if ((esc_scrap_state0_i || esc_scrap_state1_i))
-2-:	574	if ((((|state_invalid_error) | token_if_fsm_err_i) && (fsm_state_q != EscalateSt)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T4,T32,T34
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	584	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	585	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	586	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	589	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	684	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[0]))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T57,T58,T36

	LineNo.	Expression
-1-:	687	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[1]))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T57,T58,T36

	LineNo.	Expression
-1-:	691	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[2]))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T57,T58,T36

	LineNo.	Expression
-1-:	694	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[3]))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T57,T58,T36

	LineNo.	Expression
-1-:	698	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_token_valid[0]))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T57,T58,T36

	LineNo.	Expression
-1-:	701	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_token_valid[1]))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T57,T58,T36

	LineNo.	Expression
-1-:	882	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : lc_ctrl_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ClkBypStaysOnOnceAsserted_A	244210716	11871343	0	140
EscStaysOnOnceAsserted_A	244210716	41833584	0	17
FlashRmaStaysOnOnceAsserted_A	244210716	1393053	0	26
FsmStateKnown_A	244210716	235143120	0	0
LcCntKnown_A	244210716	235143120	0	0
LcStateKnown_A	244210716	235143120	0	0
NoClkBypInProdStates_A	244210716	33315392	0	0
SecCmCFILinear_A	244210716	0	0	4182
SecCmCFITerminal0_A	244210716	29312069	0	0
SecCmCFITerminal1_A	244210716	183926	0	0
SecCmCFITerminal2_A	244210716	15060265	0	0
SecCmCFITerminal3_A	244210716	26626051	0	0
u_cnt_regs_A	225981828	217862844	0	0
u_fsm_state_regs_A	238511792	229750950	0	0
u_state_regs_A	231649591	223500544	0	0

ClkBypStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	11871343	0	140
T4	508588	185233	0	0
T5	100520	98335	0	1
T6	71439	63410	0	1
T7	0	10503	0	1
T8	23548	0	0	0
T9	4732	321	0	0
T10	1547	0	0	0
T11	58216	0	0	0
T14	4885	0	0	0
T15	20023	0	0	0
T16	0	98642	0	0
T20	20641	3946	0	1
T24	0	26798	0	1
T25	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T33	0	3583	0	0
T44	0	0	0	1
T59	0	6132	0	0
T60	0	0	0	1

EscStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	41833584	0	17
T1	14688	1636	0	0
T2	1803	0	0	0
T3	2972	685	0	0
T4	508588	260421	0	0
T5	100520	0	0	0
T6	71439	0	0	0
T8	23548	1855	0	0
T9	4732	0	0	0
T10	1547	0	0	0
T11	58216	2216	0	0
T14	0	1496	0	0
T20	0	635	0	0
T21	0	5715	0	0
T22	0	7720	0	0
T32	0	16802	0	0
T37	0	0	0	1
T61	0	0	0	1
T62	0	0	0	1
T63	0	0	0	1
T64	0	0	0	1
T65	0	0	0	1
T66	0	0	0	1
T67	0	0	0	1
T68	0	0	0	1
T69	0	0	0	1

FlashRmaStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	1393053	0	26
T4	508588	27393	0	0
T5	100520	0	0	0
T6	71439	0	0	0
T8	23548	150	0	0
T9	4732	33	0	0
T10	1547	0	0	0
T11	58216	0	0	0
T14	4885	0	0	0
T15	20023	0	0	0
T17	0	490	0	0
T19	0	330	0	0
T20	20641	230	0	0
T22	0	2318	0	0
T33	0	603	0	1
T55	0	553	0	0
T57	0	702	0	0
T70	0	0	0	1
T71	0	0	0	1
T72	0	0	0	1
T73	0	0	0	1
T74	0	0	0	1
T75	0	0	0	1
T76	0	0	0	1
T77	0	0	0	1
T78	0	0	0	1

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcCntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

NoClkBypInProdStates_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	33315392	0	0
T4	508588	826772	0	0
T5	100520	0	0	0
T6	71439	0	0	0
T8	23548	1164	0	0
T9	4732	952	0	0
T10	1547	0	0	0
T11	58216	5538	0	0
T14	4885	888	0	0
T15	20023	2190	0	0
T19	0	3152	0	0
T20	20641	3048	0	0
T21	0	4540	0	0
T32	0	2593	0	0

SecCmCFILinear_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	0	0	4182

SecCmCFITerminal0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	29312069	0	0
T1	14688	2237	0	0
T2	1803	0	0	0
T3	2972	426	0	0
T4	508588	554191	0	0
T5	100520	0	0	0
T6	71439	0	0	0
T8	23548	8519	0	0
T9	4732	863	0	0
T10	1547	0	0	0
T11	58216	17027	0	0
T14	0	796	0	0
T15	0	8539	0	0
T19	0	11129	0	0
T20	0	2950	0	0

SecCmCFITerminal1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	183926	0	0
T4	508588	4994	0	0
T5	100520	0	0	0
T6	71439	0	0	0
T8	23548	0	0	0
T9	4732	0	0	0
T10	1547	0	0	0
T11	58216	0	0	0
T14	4885	0	0	0
T15	20023	0	0	0
T16	0	775	0	0
T17	0	6	0	0
T20	20641	635	0	0
T45	0	3	0	0
T46	0	6	0	0
T51	0	91	0	0
T54	0	25	0	0
T61	0	835	0	0
T79	0	874	0	0

SecCmCFITerminal2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	15060265	0	0
T1	14688	1638	0	0
T2	1803	0	0	0
T3	2972	690	0	0
T4	508588	119778	0	0
T5	100520	0	0	0
T6	71439	0	0	0
T8	23548	1870	0	0
T9	4732	0	0	0
T10	1547	0	0	0
T11	58216	2231	0	0
T14	0	1507	0	0
T21	0	5727	0	0
T22	0	7728	0	0
T32	0	10752	0	0
T34	0	6775	0	0

SecCmCFITerminal3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	26626051	0	0
T4	508588	135882	0	0
T5	100520	0	0	0
T6	71439	0	0	0
T8	23548	0	0	0
T9	4732	0	0	0
T10	1547	0	0	0
T11	58216	0	0	0
T14	4885	0	0	0
T15	20023	0	0	0
T20	20641	0	0	0
T32	0	6099	0	0
T34	0	6724	0	0
T57	0	2754	0	0
T58	0	2392	0	0
T59	0	378127	0	0
T80	0	4920	0	0
T81	0	11108	0	0
T82	0	9656	0	0
T83	0	297	0	0

u_cnt_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225981828	217862844	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	498943	493011	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

u_fsm_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238511792	229750950	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	505282	498751	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231649591	223500544	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	501203	495369	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm

	Line No.	Total	Covered	Percent
TOTAL		164	161	98.17
CONT_ASSIGN	126	1	1	100.00
ALWAYS	146	3	3	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	204	104	102	98.08
ALWAYS	584	3	3	100.00
ALWAYS	585	3	3	100.00
ALWAYS	586	3	3	100.00
ALWAYS	589	3	3	100.00
CONT_ASSIGN	623	1	0	0.00
CONT_ASSIGN	666	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
ALWAYS	677	15	15	100.00
ALWAYS	712	14	14	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	740	1	1	100.00
CONT_ASSIGN	742	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
ALWAYS	882	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
126	1	1
146	1	1
147	1	1
148	1	1
171	1	1
178	1	1
179	1	1
204	1	1
205	1	1
206	1	1
209	1	1
210	1	1
213	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
231	1	1
232	1	1
238	1	1
239	1	1
240	1	1
242	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
254	1	1
255	1	1
			MISSING_ELSE
263	1	1
273	1	1
277	1	1
278	1	1
			==> MISSING_ELSE
284	1	1
285	1	1
293	1	1
295		unreachable
299		unreachable
301		unreachable
305		unreachable
309		unreachable
312		unreachable
314		unreachable
316		unreachable
317		unreachable
321		unreachable
326	1	1
327	1	1
			MISSING_ELSE
333	1	1
350	1	1
351	1	1
			MISSING_ELSE
			MISSING_ELSE
364	1	1
365	1	1
382	1	1
383	1	1
384	1	1
385	1	1
			MISSING_ELSE
388	1	1
391	1	1
398	1	1
399	1	1
401	1	1
407	1	1
411	1	1
412	1	1
413	1	1
			MISSING_ELSE
418	1	1
419	1	1
420	1	1
421	1	1
423	1	1
			MISSING_ELSE
431	1	1
432	1	1
434	1	1
445	1	1
446	1	1
452	1	1
455	1	1
457	1	1
458	1	1
			MISSING_ELSE
466	1	1
467	1	1
468	1	1
469	1	1
			MISSING_ELSE
472	1	1
482	1	1
483	1	1
487	1	1
493	1	1
496	1	1
499	1	1
501	1	1
504	0	1
505	0	1
509	1	1
510	1	1
520	1	1
524	1	1
525	1	1
526	1	1
529	1	1
533	1	1
534	1	1
535	1	1
536	1	1
537	1	1
538	1	1
			MISSING_ELSE
544	1	1
549	1	1
554	1	1
555	1	1
567	1	1
568	1	1
574	1	1
575	1	1
576	1	1
			MISSING_ELSE
584	3	3
585	3	3
586	3	3
589	1	1
590	1	1
592	1	1
623	0	1
666	1	1
667	1	1
668	1	1
677	1	1
679	1	1
681	1	1
684	1	1
685	1	1
			MISSING_ELSE
687	1	1
688	1	1
			MISSING_ELSE
691	1	1
692	1	1
			MISSING_ELSE
694	1	1
695	1	1
			MISSING_ELSE
698	1	1
699	1	1
			MISSING_ELSE
701	1	1
702	1	1
			MISSING_ELSE
712	1	1
713	1	1
714	1	1
715	1	1
716	1	1
717	1	1
718	1	1
720	1	1
721	1	1
722	1	1
723	1	1
724	1	1
725	1	1
726	1	1
732	1	1
736	1	1
740	1	1
742	1	1
749	1	1
882	3	3

---

Cond Coverage for Instance : tb.dut.u_lc_ctrl_fsm

	Total	Covered	Percent
Conditions	72	67	93.06
Logical	72	67	93.06
Non-Logical	0	0
Event	0	0

 LINE       251
 EXPRESSION (init_req_i && lc_state_valid_q)
             -----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T32,T34
1	1	Covered	T1,T2,T3

 LINE       284
 EXPRESSION (lc_state_q == LcStScrap)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T20,T17

 LINE       295
 EXPRESSION ((lc_state_q == LcStRaw) && (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}) && ((!trans_invalid_error_o)))
             -----------1-----------    ----------------------------------------2---------------------------------------    -------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       295
 SUB-EXPRESSION (lc_state_q == LcStRaw)
                -----------1-----------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       295
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})
                ----------------------------------------1---------------------------------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       299
 EXPRESSION (unhashed_token_i == lc_ctrl_state_pkg::RndCnstRawUnlockTokenHashed)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       305
 EXPRESSION ((lc_cnt_q == LcCnt0) ? LcCnt1 : lc_cnt_q)
             ----------1---------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       305
 SUB-EXPRESSION (lc_cnt_q == LcCnt0)
                ----------1---------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       411
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[1])
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T4,T8,T11

 LINE       452
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T8,T11
1	0	1	Covered	T4,T8,T11
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T9

 LINE       452
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T4,T8,T11
1	Covered	T4,T8,T9

 LINE       466
 EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T4,T8,T9

 LINE       493
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T9

 LINE       493
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T8,T9

 LINE       496
 EXPRESSION (fsm_state_q == TokenCheck1St)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T4,T8,T9

 LINE       524
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[2])
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T4,T12,T35

 LINE       529
 EXPRESSION 
 Number  Term
      1  ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off))) || 
      2  ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T9
0	1	Covered	T4,T16,T36
1	0	Covered	T13,T37,T35

 LINE       529
 SUB-EXPRESSION ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off)))
                 -----------------------------------1----------------------------------    --------------------------------2--------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T20
1	0	Covered	T4,T8,T9
1	1	Covered	T13,T37,T35

 LINE       529
 SUB-EXPRESSION (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T4,T9,T20
1	Covered	T4,T8,T9

 LINE       529
 SUB-EXPRESSION ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off))
                 -------------1-------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T9
0	1	Covered	T13,T37,T35
1	0	Covered	T38,T39,T40

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_req_o != Off)
                -------------1-------------

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T4,T9,T20

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_ack_buf[2] != Off)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T4,T9,T20

 LINE       529
 SUB-EXPRESSION ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On)))
                 -----------------------------------1----------------------------------    -------------------------------2-------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Covered	T4,T9,T20
1	1	Covered	T4,T16,T36

 LINE       529
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T4,T8,T9
1	Covered	T4,T9,T20

 LINE       529
 SUB-EXPRESSION ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On))
                 -------------1------------    ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T20
0	1	Covered	T4,T16,T36
1	0	Covered	T41,T42,T43

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_req_o != On)
                -------------1------------

-1-	Status	Tests
0	Covered	T4,T9,T20
1	Covered	T4,T8,T9

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_ack_buf[2] != On)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T9,T20
1	Covered	T4,T8,T9

 LINE       567
 EXPRESSION (esc_scrap_state0_i || esc_scrap_state1_i)
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       574
 EXPRESSION ((((|state_invalid_error)) | token_if_fsm_err_i) && (fsm_state_q != EscalateSt))
             -----------------------1-----------------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T32,T34
1	1	Covered	T4,T32,T34

 LINE       574
 SUB-EXPRESSION (((|state_invalid_error)) | token_if_fsm_err_i)
                 ------------1-----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T32,T34
1	0	Covered	T4,T32,T34

 LINE       574
 SUB-EXPRESSION (fsm_state_q != EscalateSt)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       732
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[0]][trans_target_i[0]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       732
 SUB-EXPRESSION ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Unreachable	T5,T6,T7
1	1	Covered	T1,T2,T3

 LINE       736
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[1]][trans_target_i[1]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       736
 SUB-EXPRESSION ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Unreachable	T5,T6,T44
1	1	Covered	T1,T2,T3

 LINE       749
 EXPRESSION (trans_invalid_error || (token_idx0 != token_idx1))
             ---------1---------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T19
1	0	Covered	T4,T8,T11

 LINE       749
 SUB-EXPRESSION (token_idx0 != token_idx1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T19

---

FSM Coverage for Instance : tb.dut.u_lc_ctrl_fsm

Summary for FSM :: fsm_state_q

	Total	Covered	Percent
States	15	15	100.00	(Not included in score)
Transitions	35	34	97.14
Sequences	0	0

State, Transition and Sequence Details for FSM :: fsm_state_q

---

states	Line No.	Covered	Tests
ClkMuxSt	327	Covered	T1,T3,T4
CntIncrSt	385	Covered	T1,T3,T4
CntProgSt	401	Covered	T1,T3,T4
EscalateSt	568	Covered	T1,T3,T4
FlashRmaSt	455	Covered	T4,T8,T9
IdleSt	252	Covered	T1,T2,T3
InvalidSt	575	Covered	T4,T32,T34
PostTransSt	317	Covered	T1,T3,T4
ResetSt	246	Covered	T1,T2,T3
ScrapSt	285	Covered	T4,T20,T17
TokenCheck0St	469	Covered	T4,T8,T9
TokenCheck1St	501	Covered	T4,T8,T9
TokenHashSt	434	Covered	T4,T8,T9
TransCheckSt	423	Covered	T4,T8,T9
TransProgSt	499	Covered	T4,T8,T9

transitions	Line No.	Covered	Tests	Exclude Annotation
ClkMuxSt->CntIncrSt	385	Covered	T1,T3,T4
ClkMuxSt->EscalateSt	568	Covered	T17,T45,T46
ClkMuxSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
CntIncrSt->CntProgSt	401	Covered	T1,T3,T4
CntIncrSt->EscalateSt	568	Covered	T17,T45,T46
CntIncrSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
CntIncrSt->PostTransSt	399	Covered	T4,T8,T11
CntProgSt->EscalateSt	568	Covered	T17,T45,T46
CntProgSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
CntProgSt->PostTransSt	412	Covered	T1,T3,T4
CntProgSt->TransCheckSt	423	Covered	T4,T8,T9
EscalateSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
FlashRmaSt->EscalateSt	568	Covered	T17,T46,T47
FlashRmaSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
FlashRmaSt->TokenCheck0St	469	Covered	T4,T8,T9
IdleSt->ClkMuxSt	327	Covered	T1,T3,T4
IdleSt->EscalateSt	568	Covered	T48,T49,T50
IdleSt->InvalidSt	575	Covered	T4,T32,T34
IdleSt->PostTransSt	317	Not Covered
IdleSt->ScrapSt	285	Covered	T4,T20,T17
InvalidSt->EscalateSt	568	Covered	T4,T32,T34
PostTransSt->EscalateSt	568	Covered	T1,T3,T4
PostTransSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
ResetSt->EscalateSt	568	Covered	T17,T45,T46
ResetSt->IdleSt	252	Covered	T1,T2,T3
ResetSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
ScrapSt->EscalateSt	568	Covered	T17,T45,T46
ScrapSt->InvalidSt	575	Covered	T51,T52,T53
TokenCheck0St->EscalateSt	568	Covered	T17,T45,T48
TokenCheck0St->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TokenCheck0St->PostTransSt	483	Covered	T4,T8,T11
TokenCheck0St->TokenCheck1St	501	Covered	T4,T8,T9
TokenCheck1St->EscalateSt	568	Covered	T17,T45,T46
TokenCheck1St->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TokenCheck1St->PostTransSt	483	Covered	T4,T11,T19
TokenCheck1St->TransProgSt	499	Covered	T4,T8,T9
TokenHashSt->EscalateSt	568	Covered	T4,T17,T45
TokenHashSt->FlashRmaSt	455	Covered	T4,T8,T9
TokenHashSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TokenHashSt->PostTransSt	457	Covered	T4,T8,T11
TransCheckSt->EscalateSt	568	Covered	T17,T45,T47
TransCheckSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TransCheckSt->PostTransSt	432	Covered	T4,T8,T11
TransCheckSt->TokenHashSt	434	Covered	T4,T8,T9
TransProgSt->EscalateSt	568	Covered	T17,T45,T46
TransProgSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TransProgSt->PostTransSt	525	Covered	T4,T8,T9

Summary for FSM :: lc_state_q

	Total	Covered	Percent
States	21	12	57.14	(Not included in score)
Transitions	1	1	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_state_q

---

states	Line No.	Covered	Tests
LcStDev	92	Not Covered
LcStProd	93	Not Covered
LcStProdEnd	94	Not Covered
LcStRaw	295	Covered	T2,T4,T8
LcStRma	333	Not Covered
LcStScrap	284	Not Covered
LcStTestLocked0	333	Covered	T4,T8,T9
LcStTestLocked1	333	Covered	T4,T8,T11
LcStTestLocked2	333	Covered	T1,T3,T4
LcStTestLocked3	333	Covered	T4,T8,T9
LcStTestLocked4	333	Covered	T4,T8,T9
LcStTestLocked5	333	Not Covered
LcStTestLocked6	333	Not Covered
LcStTestUnlocked0	301	Covered	T4,T8,T9
LcStTestUnlocked1	333	Covered	T3,T4,T8
LcStTestUnlocked2	333	Covered	T3,T4,T9
LcStTestUnlocked3	333	Covered	T3,T4,T8
LcStTestUnlocked4	333	Covered	T4,T8,T9
LcStTestUnlocked5	333	Covered	T1,T3,T4
LcStTestUnlocked6	333	Not Covered
LcStTestUnlocked7	333	Not Covered

transitions	Line No.	Covered	Tests
LcStRaw->LcStTestUnlocked0	301	Covered	T4,T8,T17

Summary for FSM :: lc_cnt_q

	Total	Covered	Percent
States	25	6	24.00	(Not included in score)
Transitions	1	1	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_cnt_q

---

states	Line No.	Covered	Tests
LcCnt0	305	Covered	T4,T8,T12
LcCnt1	305	Covered	T4,T8,T11
LcCnt10	112	Not Covered
LcCnt11	113	Not Covered
LcCnt12	114	Not Covered
LcCnt13	115	Not Covered
LcCnt14	116	Not Covered
LcCnt15	117	Not Covered
LcCnt16	118	Not Covered
LcCnt17	119	Not Covered
LcCnt18	120	Not Covered
LcCnt19	121	Not Covered
LcCnt2	104	Covered	T4,T8,T11
LcCnt20	122	Not Covered
LcCnt21	123	Not Covered
LcCnt22	124	Not Covered
LcCnt23	125	Not Covered
LcCnt24	126	Not Covered
LcCnt3	105	Covered	T2,T4,T8
LcCnt4	106	Covered	T4,T8,T9
LcCnt5	107	Covered	T4,T8,T9
LcCnt6	108	Not Covered
LcCnt7	109	Not Covered
LcCnt8	110	Not Covered
LcCnt9	111	Not Covered

transitions	Line No.	Covered	Tests
LcCnt0->LcCnt1	305	Covered	T8,T12,T37

---

Branch Coverage for Instance : tb.dut.u_lc_ctrl_fsm

	Line No.	Total	Covered	Percent
Branches		69	67	97.10
TERNARY	732	1	1	100.00
TERNARY	736	1	1	100.00
CASE	242	42	40	95.24
IF	567	3	3	100.00
IF	584	2	2	100.00
IF	585	2	2	100.00
IF	586	2	2	100.00
IF	589	2	2	100.00
IF	684	2	2	100.00
IF	687	2	2	100.00
IF	691	2	2	100.00
IF	694	2	2	100.00
IF	698	2	2	100.00
IF	701	2	2	100.00
IF	882	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	732	(((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

	LineNo.	Expression
-1-:	736	(((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

	LineNo.	Expression
-1-:	242	case (fsm_state_q)
-2-:	251	if ((init_req_i && lc_state_valid_q))
-3-:	273	if (((!((SecVolatileRawUnlockEn && (lc_state_q == LcStTestUnlocked0)) && (lc_cnt_q != LcCnt0))) || prim_mubi_pkg::mubi8_test_false_loose(volatile_raw_unlock_success_q)))
-4-:	284	if ((lc_state_q == LcStScrap))
-5-:	293	if (((SecVolatileRawUnlockEn && volatile_raw_unlock_i) && trans_cmd_i))
-6-:	295	if ((((lc_state_q == LcStRaw) && (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})) && (!trans_invalid_error_o)))
-7-:	299	if ((unhashed_token_i == lc_ctrl_state_pkg::RndCnstRawUnlockTokenHashed))
-8-:	305	((lc_cnt_q == LcCnt0)) ? 
-9-:	326	if (trans_cmd_i)
-10-:	333	if ((lc_state_q inside {LcStRaw, LcStTestLocked0, LcStTestLocked1, LcStTestLocked2, LcStTestLocked3, LcStTestLocked4, LcStTestLocked5, LcStTestLocked6, LcStTestUnlocked0, LcStTestUnlocked1, LcStTestUnlocked2, LcStTestUnlocked3, LcStTestUnlocked4, LcStTestUnlocked5, LcStTestUnlocked6, LcStTestUnlocked7, LcStRma}))
-11-:	350	if (use_ext_clock_i)
-12-:	365	if ((lc_state_q inside {LcStRaw, LcStTestLocked0, LcStTestLocked1, LcStTestLocked2, LcStTestLocked3, LcStTestLocked4, LcStTestLocked5, LcStTestLocked6, LcStTestUnlocked0, LcStTestUnlocked1, LcStTestUnlocked2, LcStTestUnlocked3, LcStTestUnlocked4, LcStTestUnlocked5, LcStTestUnlocked6, LcStTestUnlocked7, LcStRma}))
-13-:	382	if (use_ext_clock_i)
-14-:	384	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_clk_byp_ack[0]))
-15-:	398	if (trans_cnt_oflw_error_o)
-16-:	411	if ((lc_clk_byp_req_o != lc_clk_byp_ack[1]))
-17-:	418	if (otp_prog_ack_i)
-18-:	419	if (otp_prog_err_i)
-19-:	431	if (trans_invalid_error_o)
-20-:	446	if (token_hash_ack_i)
-21-:	452	if ((((hashed_token_i == hashed_token_mux) && (!token_hash_err_i)) && (&hashed_token_valid_mux)))
-22-:	466	if ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}))
-23-:	468	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_ack_buf[0]))
-24-:	482	if (trans_invalid_error_o)
-25-:	487	if (((((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_flash_rma_req_o)) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_flash_rma_ack_buf[1])) || (((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_req_o)) && lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_ack_buf[1]))))
-26-:	493	if ((((hashed_token_i == hashed_token_mux) && (!token_hash_err_i)) && (&hashed_token_valid_mux)))
-27-:	496	if ((fsm_state_q == TokenCheck1St))
-28-:	524	if ((lc_clk_byp_req_o != lc_clk_byp_ack[2]))
-29-:	529	if ((((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off))) || ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On)))))
-30-:	535	if (otp_prog_ack_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T17
IdleSt	-	-	0	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IdleSt	-	-	0	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IdleSt	-	-	0	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IdleSt	-	-	0	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IdleSt	-	-	0	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	0	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T5
IdleSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T20
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T54,T37
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T11
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T11
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T11
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T11
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	Covered	T4,T8,T9
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	Covered	T4,T8,T9
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T19,T55,T56
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	1	-	-	-	Covered	T4,T8,T9
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	0	-	-	-	Covered	T4,T8,T9
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	-	-	-	-	Not Covered
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T8,T11
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T12,T35
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T16,T13
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	1	Covered	T4,T8,T9
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	Covered	T4,T8,T9
ScrapSt PostTransSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
EscalateSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
InvalidSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T32,T34
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T32,T34

	LineNo.	Expression
-1-:	567	if ((esc_scrap_state0_i || esc_scrap_state1_i))
-2-:	574	if ((((|state_invalid_error) | token_if_fsm_err_i) && (fsm_state_q != EscalateSt)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T4,T32,T34
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	584	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	585	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	586	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	589	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	684	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[0]))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T57,T58,T36

	LineNo.	Expression
-1-:	687	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[1]))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T57,T58,T36

	LineNo.	Expression
-1-:	691	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[2]))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T57,T58,T36

	LineNo.	Expression
-1-:	694	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[3]))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T57,T58,T36

	LineNo.	Expression
-1-:	698	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_token_valid[0]))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T57,T58,T36

	LineNo.	Expression
-1-:	701	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_token_valid[1]))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T57,T58,T36

	LineNo.	Expression
-1-:	882	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_lc_ctrl_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ClkBypStaysOnOnceAsserted_A	244210716	11871343	0	140
EscStaysOnOnceAsserted_A	244210716	41833584	0	17
FlashRmaStaysOnOnceAsserted_A	244210716	1393053	0	26
FsmStateKnown_A	244210716	235143120	0	0
LcCntKnown_A	244210716	235143120	0	0
LcStateKnown_A	244210716	235143120	0	0
NoClkBypInProdStates_A	244210716	33315392	0	0
SecCmCFILinear_A	244210716	0	0	4182
SecCmCFITerminal0_A	244210716	29312069	0	0
SecCmCFITerminal1_A	244210716	183926	0	0
SecCmCFITerminal2_A	244210716	15060265	0	0
SecCmCFITerminal3_A	244210716	26626051	0	0
u_cnt_regs_A	225981828	217862844	0	0
u_fsm_state_regs_A	238511792	229750950	0	0
u_state_regs_A	231649591	223500544	0	0

ClkBypStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	11871343	0	140
T4	508588	185233	0	0
T5	100520	98335	0	1
T6	71439	63410	0	1
T7	0	10503	0	1
T8	23548	0	0	0
T9	4732	321	0	0
T10	1547	0	0	0
T11	58216	0	0	0
T14	4885	0	0	0
T15	20023	0	0	0
T16	0	98642	0	0
T20	20641	3946	0	1
T24	0	26798	0	1
T25	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T33	0	3583	0	0
T44	0	0	0	1
T59	0	6132	0	0
T60	0	0	0	1

EscStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	41833584	0	17
T1	14688	1636	0	0
T2	1803	0	0	0
T3	2972	685	0	0
T4	508588	260421	0	0
T5	100520	0	0	0
T6	71439	0	0	0
T8	23548	1855	0	0
T9	4732	0	0	0
T10	1547	0	0	0
T11	58216	2216	0	0
T14	0	1496	0	0
T20	0	635	0	0
T21	0	5715	0	0
T22	0	7720	0	0
T32	0	16802	0	0
T37	0	0	0	1
T61	0	0	0	1
T62	0	0	0	1
T63	0	0	0	1
T64	0	0	0	1
T65	0	0	0	1
T66	0	0	0	1
T67	0	0	0	1
T68	0	0	0	1
T69	0	0	0	1

FlashRmaStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	1393053	0	26
T4	508588	27393	0	0
T5	100520	0	0	0
T6	71439	0	0	0
T8	23548	150	0	0
T9	4732	33	0	0
T10	1547	0	0	0
T11	58216	0	0	0
T14	4885	0	0	0
T15	20023	0	0	0
T17	0	490	0	0
T19	0	330	0	0
T20	20641	230	0	0
T22	0	2318	0	0
T33	0	603	0	1
T55	0	553	0	0
T57	0	702	0	0
T70	0	0	0	1
T71	0	0	0	1
T72	0	0	0	1
T73	0	0	0	1
T74	0	0	0	1
T75	0	0	0	1
T76	0	0	0	1
T77	0	0	0	1
T78	0	0	0	1

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcCntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

LcStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	235143120	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	508588	501749	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

NoClkBypInProdStates_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	33315392	0	0
T4	508588	826772	0	0
T5	100520	0	0	0
T6	71439	0	0	0
T8	23548	1164	0	0
T9	4732	952	0	0
T10	1547	0	0	0
T11	58216	5538	0	0
T14	4885	888	0	0
T15	20023	2190	0	0
T19	0	3152	0	0
T20	20641	3048	0	0
T21	0	4540	0	0
T32	0	2593	0	0

SecCmCFILinear_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	0	0	4182

SecCmCFITerminal0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	29312069	0	0
T1	14688	2237	0	0
T2	1803	0	0	0
T3	2972	426	0	0
T4	508588	554191	0	0
T5	100520	0	0	0
T6	71439	0	0	0
T8	23548	8519	0	0
T9	4732	863	0	0
T10	1547	0	0	0
T11	58216	17027	0	0
T14	0	796	0	0
T15	0	8539	0	0
T19	0	11129	0	0
T20	0	2950	0	0

SecCmCFITerminal1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	183926	0	0
T4	508588	4994	0	0
T5	100520	0	0	0
T6	71439	0	0	0
T8	23548	0	0	0
T9	4732	0	0	0
T10	1547	0	0	0
T11	58216	0	0	0
T14	4885	0	0	0
T15	20023	0	0	0
T16	0	775	0	0
T17	0	6	0	0
T20	20641	635	0	0
T45	0	3	0	0
T46	0	6	0	0
T51	0	91	0	0
T54	0	25	0	0
T61	0	835	0	0
T79	0	874	0	0

SecCmCFITerminal2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	15060265	0	0
T1	14688	1638	0	0
T2	1803	0	0	0
T3	2972	690	0	0
T4	508588	119778	0	0
T5	100520	0	0	0
T6	71439	0	0	0
T8	23548	1870	0	0
T9	4732	0	0	0
T10	1547	0	0	0
T11	58216	2231	0	0
T14	0	1507	0	0
T21	0	5727	0	0
T22	0	7728	0	0
T32	0	10752	0	0
T34	0	6775	0	0

SecCmCFITerminal3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244210716	26626051	0	0
T4	508588	135882	0	0
T5	100520	0	0	0
T6	71439	0	0	0
T8	23548	0	0	0
T9	4732	0	0	0
T10	1547	0	0	0
T11	58216	0	0	0
T14	4885	0	0	0
T15	20023	0	0	0
T20	20641	0	0	0
T32	0	6099	0	0
T34	0	6724	0	0
T57	0	2754	0	0
T58	0	2392	0	0
T59	0	378127	0	0
T80	0	4920	0	0
T81	0	11108	0	0
T82	0	9656	0	0
T83	0	297	0	0

u_cnt_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225981828	217862844	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	498943	493011	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

u_fsm_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238511792	229750950	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	505282	498751	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231649591	223500544	0	0
T1	14688	14467	0	0
T2	1803	1743	0	0
T3	2972	2543	0	0
T4	501203	495369	0	0
T5	100520	100428	0	0
T6	71439	71387	0	0
T8	23548	18495	0	0
T9	4732	3450	0	0
T10	1547	1486	0	0
T11	58216	50685	0	0