Module Definition
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Module : prim_sync_reqack_data
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.41 98.18 100.00 95.45 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 u_lc_ctrl_kmac_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 98.16 97.92 100.00 94.74 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
ALWAYS8344100.00
CONT_ASSIGN8911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
80 1 1
81 1 1
83 1 1
84 1 1
85 1 1
86 1 1
MISSING_ELSE
89 1 1


Cond Coverage for Module : prim_sync_reqack_data
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       80
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01CoveredT3,T50,T63
10CoveredT2,T3,T11
11CoveredT2,T3,T11

Branch Coverage for Module : prim_sync_reqack_data
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 83 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 83 if ((!rst_dst_ni)) -2-: 85 if (gen_data_reg.data_we)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T11
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%