LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: 41bc3e0c7f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.920s	1.553ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.250s	18.247us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.120s	18.557us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.020s	51.808us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.870s	41.249us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.280s	112.865us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.120s	18.557us	20	20	100.00
		lc_ctrl_csr_aliasing	1.870s	41.249us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.110s	613.011us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.640s	826.763us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	13.361us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.620s	116.818us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.620s	343.041us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	18.840s	1.730ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.620s	343.041us	50	50	100.00
		lc_ctrl_prog_failure	4.620s	116.818us	50	50	100.00
		lc_ctrl_errors	18.840s	1.730ms	50	50	100.00
		lc_ctrl_security_escalation	18.830s	2.152ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.301m	21.844ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.150s	549.496us	20	20	100.00
		lc_ctrl_jtag_errors	1.773m	8.462ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.010s	622.881us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	34.160s	3.750ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.150s	549.496us	20	20	100.00
		lc_ctrl_jtag_errors	1.773m	8.462ms	19	20	95.00
		lc_ctrl_jtag_access	18.440s	1.640ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	41.130s	2.690ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.040s	974.255us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.260s	116.179us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	32.070s	1.336ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.440s	574.499us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.560s	21.786us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.890s	831.982us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.100s	391.503us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	13.360s	5.576ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.330s	63.025us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	11.734m	51.179ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.490s	57.059us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.200s	524.108us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.200s	524.108us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.250s	18.247us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	18.557us	20	20	100.00
		lc_ctrl_csr_aliasing	1.870s	41.249us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.100s	231.264us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.250s	18.247us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	18.557us	20	20	100.00
		lc_ctrl_csr_aliasing	1.870s	41.249us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.100s	231.264us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	33.320s	794.651us	5	5	100.00
		lc_ctrl_tl_intg_err	4.560s	134.753us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.560s	134.753us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.640s	826.763us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.620s	343.041us	50	50	100.00
		lc_ctrl_sec_cm	33.320s	794.651us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.620s	343.041us	50	50	100.00
		lc_ctrl_sec_cm	33.320s	794.651us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.620s	343.041us	50	50	100.00
		lc_ctrl_sec_cm	33.320s	794.651us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.620s	343.041us	50	50	100.00
		lc_ctrl_sec_cm	33.320s	794.651us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.620s	343.041us	50	50	100.00
		lc_ctrl_sec_cm	33.320s	794.651us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.620s	343.041us	50	50	100.00
		lc_ctrl_sec_cm	33.320s	794.651us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.620s	343.041us	50	50	100.00
		lc_ctrl_sec_cm	33.320s	794.651us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.620s	343.041us	50	50	100.00
		lc_ctrl_sec_cm	33.320s	794.651us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.830s	2.152ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.110s	613.011us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	34.160s	3.750ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.830s	961.688us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.830s	961.688us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	18.570s	444.320us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.950s	1.704ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.950s	1.704ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.182h	62.183ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			999	1030	96.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.13	97.82	95.38	93.31	100.00	98.52	98.76	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.14046660018611330393698105122798500513383853185304065162175554983822241650553
      Line 326, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 720139402 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 720139402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.106112409521190201896756815065351467150852390236916154783348811646631320824839
      Line 3088, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11917904586 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 11917904586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.11496901219542292440383644511567938843831009137324683957870598830995040135317
      Line 17967, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7122121053 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 7122121053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 48.lc_ctrl_stress_all_with_rand_reset.97402906890696628662928558127553119903676958832153759725104642251622690502356
      Line 12382, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17892211651 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 17892211651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 11.lc_ctrl_jtag_errors.69956080831697900361437732649844054981535027390511984620981541067542363932141
      Line 4214, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 8462441169 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 8462441169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 22.lc_ctrl_stress_all_with_rand_reset.42008834738931387023323315921371350456477614046024554148847551909482621095593
      Line 20199, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 64963712536 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 64963712536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 29.lc_ctrl_stress_all_with_rand_reset.110648772457612060142668446294485279575871479375117995496496595707836808973
      Line 6359, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4107151473 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 4107151473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 23.lc_ctrl_stress_all_with_rand_reset.56025664075666592544555266344647220182346650061703890963910888151395496165122
      Line 13879, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 128775426179 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 128775426179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 43.lc_ctrl_stress_all_with_rand_reset.51997443605438214076063352919914683933898109398183816244985252713715878066469
      Line 47292, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

• Latest
• 2024.04.22_07.24.48