Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1783421	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2008335

1

T1

227

T3

1676

T9

1043

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3441101	1			T1	169		T3	2089		T9	1100
values[0x0]	174978	1			T1	89		T3	393		T9	318
values[0x1]	175677	1			T1	79		T3	367		T9	274

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1417165	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2374591

1

T1

254

T3

1928

T9

1181

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8800	1			T9	4		T10	3		T4	27
valid_sources[0x01]	9039	1			T9	6		T10	4		T4	41
valid_sources[0x02]	9171	1			T9	7		T10	3		T4	21
valid_sources[0x03]	34060	1			T9	7		T10	6		T4	33
valid_sources[0x04]	9029	1			T9	7		T10	8		T4	42
valid_sources[0x05]	8640	1			T9	3		T10	4		T4	41
valid_sources[0x06]	13061	1			T9	6		T10	4		T4	30
valid_sources[0x07]	17733	1			T9	4		T10	3		T4	17
valid_sources[0x08]	9264	1			T9	5		T10	11		T4	13
valid_sources[0x09]	32817	1			T9	7		T10	11		T4	73
valid_sources[0x0a]	9933	1			T9	6		T10	8		T4	34
valid_sources[0x0b]	9083	1			T9	5		T10	5		T4	50
valid_sources[0x0c]	9149	1			T9	2		T10	4		T4	47
valid_sources[0x0d]	9822	1			T9	7		T10	4		T4	52
valid_sources[0x0e]	9121	1			T9	6		T10	7		T4	33
valid_sources[0x0f]	62900	1			T9	5		T10	7		T4	57
valid_sources[0x10]	8892	1			T9	10		T10	8		T4	37
valid_sources[0x11]	10653	1			T10	5		T4	51		T13	6
valid_sources[0x12]	9462	1			T9	9		T10	5		T4	19
valid_sources[0x13]	8692	1			T9	4		T10	7		T4	29
valid_sources[0x14]	8930	1			T9	10		T10	4		T4	69
valid_sources[0x15]	10180	1			T9	6		T10	5		T4	18
valid_sources[0x16]	11666	1			T9	6		T10	5		T4	11
valid_sources[0x17]	9090	1			T9	4		T10	5		T4	50
valid_sources[0x18]	8966	1			T9	2		T10	3		T4	41
valid_sources[0x19]	8932	1			T9	6		T10	5		T4	21
valid_sources[0x1a]	9954	1			T9	8		T10	5		T4	15
valid_sources[0x1b]	8577	1			T9	3		T10	5		T4	18
valid_sources[0x1c]	10084	1			T9	5		T10	8		T4	46
valid_sources[0x1d]	12739	1			T9	7		T10	4		T4	36
valid_sources[0x1e]	8559	1			T9	14		T10	8		T4	8
valid_sources[0x1f]	9236	1			T1	337		T9	5		T10	3
valid_sources[0x20]	12842	1			T9	10		T10	5		T4	2
valid_sources[0x21]	30041	1			T9	6		T10	6		T4	78
valid_sources[0x22]	8667	1			T9	3		T10	4		T4	37
valid_sources[0x23]	8704	1			T9	7		T10	3		T4	27
valid_sources[0x24]	9176	1			T9	9		T10	6		T4	14
valid_sources[0x25]	13032	1			T9	4		T10	2		T4	11
valid_sources[0x26]	9081	1			T9	7		T10	5		T4	45
valid_sources[0x27]	9860	1			T9	4		T10	2		T4	57
valid_sources[0x28]	10822	1			T9	3		T10	2		T4	47
valid_sources[0x29]	9451	1			T9	10		T10	5		T4	52
valid_sources[0x2a]	9089	1			T9	3		T10	10		T4	39
valid_sources[0x2b]	8877	1			T9	8		T10	9		T4	72
valid_sources[0x2c]	9043	1			T9	9		T10	5		T4	39
valid_sources[0x2d]	9067	1			T9	5		T10	7		T4	24
valid_sources[0x2e]	14885	1			T9	4		T10	3		T4	24
valid_sources[0x2f]	8996	1			T9	6		T10	10		T4	9
valid_sources[0x30]	53878	1			T9	7		T10	4		T4	83
valid_sources[0x31]	8626	1			T9	10		T10	3		T4	35
valid_sources[0x32]	9883	1			T9	6		T10	4		T4	32
valid_sources[0x33]	8891	1			T9	5		T10	3		T4	3
valid_sources[0x34]	8805	1			T9	10		T10	3		T4	26
valid_sources[0x35]	8767	1			T9	4		T10	1		T4	31
valid_sources[0x36]	9240	1			T9	12		T10	8		T4	39
valid_sources[0x37]	8599	1			T9	6		T10	7		T4	45
valid_sources[0x38]	8739	1			T9	10		T10	4		T4	25
valid_sources[0x39]	8919	1			T9	7		T10	7		T4	40
valid_sources[0x3a]	9236	1			T9	10		T10	5		T4	35
valid_sources[0x3b]	9142	1			T9	6		T10	6		T4	66
valid_sources[0x3c]	8689	1			T9	15		T10	3		T4	51
valid_sources[0x3d]	107538	1			T9	6		T10	6		T4	62
valid_sources[0x3e]	9751	1			T9	5		T10	3		T4	42
valid_sources[0x3f]	8783	1			T9	8		T10	4		T4	42
valid_sources[0x40]	13308	1			T9	6		T10	2		T4	32
valid_sources[0x41]	8856	1			T9	6		T10	8		T4	57
valid_sources[0x42]	12447	1			T9	9		T10	3		T4	61
valid_sources[0x43]	20434	1			T9	6		T10	4		T4	36
valid_sources[0x44]	46719	1			T9	6		T10	7		T4	66
valid_sources[0x45]	8607	1			T9	4		T10	8		T4	34
valid_sources[0x46]	8453	1			T9	4		T10	5		T4	52
valid_sources[0x47]	8915	1			T9	12		T10	8		T4	52
valid_sources[0x48]	8739	1			T9	9		T10	1		T4	15
valid_sources[0x49]	8788	1			T9	2		T10	10		T4	27
valid_sources[0x4a]	11641	1			T9	6		T10	7		T4	52
valid_sources[0x4b]	8765	1			T9	6		T10	9		T4	20
valid_sources[0x4c]	27199	1			T9	6		T10	5		T4	22
valid_sources[0x4d]	8943	1			T9	8		T10	9		T4	32
valid_sources[0x4e]	8854	1			T9	6		T10	6		T4	29
valid_sources[0x4f]	8510	1			T9	4		T10	3		T4	15
valid_sources[0x50]	8855	1			T9	3		T10	5		T4	19
valid_sources[0x51]	12466	1			T9	12		T10	8		T4	26
valid_sources[0x52]	22052	1			T9	3		T10	7		T4	59
valid_sources[0x53]	8484	1			T9	5		T10	4		T4	19
valid_sources[0x54]	9854	1			T9	7		T10	9		T4	20
valid_sources[0x55]	22657	1			T9	8		T10	8		T4	15
valid_sources[0x56]	8571	1			T9	13		T10	6		T4	18
valid_sources[0x57]	8897	1			T9	8		T10	4		T4	30
valid_sources[0x58]	10437	1			T9	8		T10	4		T4	36
valid_sources[0x59]	9460	1			T9	6		T10	6		T4	32
valid_sources[0x5a]	182598	1			T9	5		T10	4		T4	50
valid_sources[0x5b]	9260	1			T9	7		T10	6		T4	39
valid_sources[0x5c]	9080	1			T9	6		T10	7		T4	9
valid_sources[0x5d]	9261	1			T9	10		T10	6		T4	39
valid_sources[0x5e]	8675	1			T9	8		T10	5		T4	24
valid_sources[0x5f]	11265	1			T9	8		T10	7		T4	33
valid_sources[0x60]	8963	1			T9	15		T10	5		T4	49
valid_sources[0x61]	8828	1			T9	10		T10	3		T4	28
valid_sources[0x62]	8712	1			T9	5		T10	6		T4	21
valid_sources[0x63]	8327	1			T9	8		T10	5		T4	50
valid_sources[0x64]	10696	1			T9	6		T10	5		T4	47
valid_sources[0x65]	9736	1			T9	5		T10	8		T4	46
valid_sources[0x66]	8900	1			T9	5		T10	5		T4	52
valid_sources[0x67]	8911	1			T9	3		T10	4		T4	55
valid_sources[0x68]	9265	1			T9	8		T10	7		T4	23
valid_sources[0x69]	18167	1			T9	9		T10	8		T4	42
valid_sources[0x6a]	10581	1			T9	4		T10	6		T4	28
valid_sources[0x6b]	71770	1			T9	13		T10	3		T4	59
valid_sources[0x6c]	9842	1			T9	8		T10	7		T4	29
valid_sources[0x6d]	8791	1			T9	1		T10	2		T4	68
valid_sources[0x6e]	11874	1			T9	5		T10	9		T4	18
valid_sources[0x6f]	11606	1			T9	6		T10	6		T4	7
valid_sources[0x70]	8975	1			T9	6		T10	6		T4	42
valid_sources[0x71]	13570	1			T9	7		T10	4		T4	34
valid_sources[0x72]	8813	1			T9	2		T4	53		T13	8
valid_sources[0x73]	9031	1			T9	4		T10	9		T4	23
valid_sources[0x74]	22257	1			T9	5		T10	6		T4	21
valid_sources[0x75]	9732	1			T9	9		T10	3		T4	65
valid_sources[0x76]	8967	1			T9	7		T10	4		T4	36
valid_sources[0x77]	9037	1			T9	6		T10	6		T4	59
valid_sources[0x78]	8615	1			T9	13		T10	8		T4	55
valid_sources[0x79]	80465	1			T9	7		T10	6		T4	34
valid_sources[0x7a]	12989	1			T9	8		T10	3		T4	31
valid_sources[0x7b]	114714	1			T9	10		T10	10		T4	42
valid_sources[0x7c]	8495	1			T9	6		T10	10		T4	57
valid_sources[0x7d]	8846	1			T9	5		T10	2		T4	35
valid_sources[0x7e]	8660	1			T9	9		T10	9		T4	20
valid_sources[0x7f]	9453	1			T9	8		T10	8		T4	14
valid_sources[0x80]	89164	1			T9	9		T10	9		T4	41

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1706042

1

T1

79

T3

1020

T9

526

values[0x0]

all_enables

biggest_size

151703

1

T1

80

T3

341

T9

276

values[0x1]

all_enables

biggest_size

150590

1

T1

68

T3

315

T9

241