Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	109823701	14623	0	0
claim_transition_if_regwen_rd_A	109823701	985	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109823701	14623	0	0
T7	39368	0	0	0
T23	350934	15	0	0
T42	0	2	0	0
T45	0	3	0	0
T46	34271	0	0	0
T47	24805	0	0	0
T60	9596	0	0	0
T74	0	5	0	0
T106	0	2	0	0
T107	0	1	0	0
T118	0	12	0	0
T149	0	5	0	0
T150	0	3	0	0
T151	0	4	0	0
T152	47755	0	0	0
T153	36390	0	0	0
T154	18298	0	0	0
T155	6998	0	0	0
T156	22361	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109823701	985	0	0
T45	137350	8	0	0
T86	0	6	0	0
T106	0	2	0	0
T119	0	15	0	0
T150	0	13	0	0
T151	0	3	0	0
T157	0	12	0	0
T158	0	5	0	0
T159	0	9	0	0
T160	0	9	0	0
T161	292584	0	0	0
T162	5419	0	0	0
T163	22982	0	0	0
T164	31275	0	0	0
T165	86529	0	0	0
T166	48039	0	0	0
T167	30790	0	0	0
T168	32061	0	0	0
T169	25036	0	0	0