Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2075977	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2309323

1

T1

491

T3

57

T8

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4018906	1			T1	748		T3	51		T9	522
values[0x0]	183090	1			T1	82		T3	20		T8	24
values[0x1]	183304	1			T1	78		T3	23		T8	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1649596	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2735704

1

T1

588

T3

64

T8

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13513	1			T1	3		T9	4		T11	4
valid_sources[0x01]	13669	1			T1	1		T9	4		T11	6
valid_sources[0x02]	13198	1			T1	1		T9	5		T11	3
valid_sources[0x03]	13614	1			T1	4		T9	5		T11	2
valid_sources[0x04]	13618	1			T1	11		T9	10		T11	2
valid_sources[0x05]	13232	1			T1	5		T3	6		T9	6
valid_sources[0x06]	25860	1			T1	5		T9	3		T11	3
valid_sources[0x07]	16104	1			T1	2		T9	1		T11	1
valid_sources[0x08]	12983	1			T1	4		T9	4		T12	11
valid_sources[0x09]	14018	1			T1	3		T9	5		T11	1
valid_sources[0x0a]	14378	1			T9	6		T11	3		T12	14
valid_sources[0x0b]	17546	1			T1	3		T9	6		T11	4
valid_sources[0x0c]	14787	1			T1	2		T9	2		T10	1
valid_sources[0x0d]	17439	1			T1	4		T9	2		T11	1
valid_sources[0x0e]	14702	1			T1	5		T9	6		T11	1
valid_sources[0x0f]	13378	1			T1	3		T9	2		T11	1
valid_sources[0x10]	13485	1			T1	5		T9	4		T11	1
valid_sources[0x11]	13021	1			T8	1		T9	3		T11	2
valid_sources[0x12]	13715	1			T9	3		T11	5		T12	4
valid_sources[0x13]	14456	1			T1	3		T9	5		T11	1
valid_sources[0x14]	13315	1			T9	5		T11	2		T12	6
valid_sources[0x15]	13403	1			T1	5		T9	3		T12	8
valid_sources[0x16]	13376	1			T1	5		T9	2		T11	5
valid_sources[0x17]	15254	1			T1	2		T9	4		T11	2
valid_sources[0x18]	14818	1			T1	2		T8	1		T9	9
valid_sources[0x19]	13188	1			T1	6		T9	4		T11	3
valid_sources[0x1a]	18833	1			T1	8		T9	12		T11	1
valid_sources[0x1b]	13554	1			T1	5		T9	4		T11	3
valid_sources[0x1c]	13401	1			T1	3		T9	3		T11	2
valid_sources[0x1d]	13506	1			T1	3		T11	3		T12	8
valid_sources[0x1e]	14037	1			T1	2		T9	4		T11	1
valid_sources[0x1f]	13767	1			T1	4		T9	3		T11	4
valid_sources[0x20]	13599	1			T1	7		T9	8		T12	9
valid_sources[0x21]	15386	1			T1	2		T9	7		T11	2
valid_sources[0x22]	13182	1			T1	4		T9	5		T12	9
valid_sources[0x23]	13164	1			T1	3		T9	3		T11	4
valid_sources[0x24]	13231	1			T1	8		T9	4		T11	1
valid_sources[0x25]	13439	1			T1	6		T8	1		T9	8
valid_sources[0x26]	13562	1			T1	5		T9	6		T10	2
valid_sources[0x27]	13554	1			T1	11		T11	1		T12	6
valid_sources[0x28]	14682	1			T1	6		T9	3		T11	3
valid_sources[0x29]	25857	1			T1	3		T9	7		T12	12
valid_sources[0x2a]	13363	1			T1	6		T11	1		T12	14
valid_sources[0x2b]	14007	1			T1	2		T9	1		T11	3
valid_sources[0x2c]	14547	1			T1	4		T9	5		T11	2
valid_sources[0x2d]	13225	1			T1	3		T9	3		T11	1
valid_sources[0x2e]	13504	1			T1	2		T9	3		T11	3
valid_sources[0x2f]	12842	1			T1	3		T9	2		T11	1
valid_sources[0x30]	12716	1			T1	1		T9	1		T11	1
valid_sources[0x31]	14399	1			T1	3		T9	4		T11	2
valid_sources[0x32]	13606	1			T1	1		T9	9		T11	2
valid_sources[0x33]	13282	1			T9	3		T11	2		T12	7
valid_sources[0x34]	14626	1			T9	3		T11	5		T12	7
valid_sources[0x35]	13555	1			T1	3		T9	4		T11	1
valid_sources[0x36]	13307	1			T1	2		T11	3		T12	11
valid_sources[0x37]	12989	1			T1	5		T11	2		T12	11
valid_sources[0x38]	13449	1			T1	7		T9	2		T10	1
valid_sources[0x39]	15757	1			T1	2		T3	8		T9	4
valid_sources[0x3a]	13841	1			T1	8		T3	3		T9	6
valid_sources[0x3b]	13337	1			T1	6		T11	1		T12	7
valid_sources[0x3c]	13606	1			T1	2		T9	3		T10	1
valid_sources[0x3d]	13063	1			T1	2		T9	1		T11	4
valid_sources[0x3e]	13327	1			T1	2		T8	1		T9	4
valid_sources[0x3f]	13595	1			T1	6		T11	4		T12	14
valid_sources[0x40]	13561	1			T1	7		T9	1		T12	14
valid_sources[0x41]	13525	1			T1	3		T9	2		T11	1
valid_sources[0x42]	14664	1			T1	2		T8	1		T9	6
valid_sources[0x43]	13634	1			T1	5		T9	10		T11	1
valid_sources[0x44]	33679	1			T1	3		T8	1		T9	4
valid_sources[0x45]	13592	1			T1	4		T8	4		T9	2
valid_sources[0x46]	14111	1			T1	3		T9	6		T10	1
valid_sources[0x47]	26040	1			T1	6		T9	6		T12	8
valid_sources[0x48]	186814	1			T1	3		T3	3		T9	4
valid_sources[0x49]	13383	1			T1	4		T9	3		T11	2
valid_sources[0x4a]	13627	1			T1	8		T9	4		T11	2
valid_sources[0x4b]	14600	1			T1	3		T9	2		T11	2
valid_sources[0x4c]	13365	1			T1	3		T9	3		T11	2
valid_sources[0x4d]	12964	1			T9	1		T11	3		T12	11
valid_sources[0x4e]	13039	1			T1	1		T9	2		T12	12
valid_sources[0x4f]	13377	1			T1	4		T9	4		T11	1
valid_sources[0x50]	13813	1			T1	6		T9	6		T11	3
valid_sources[0x51]	13368	1			T1	5		T9	1		T11	5
valid_sources[0x52]	13200	1			T1	4		T9	5		T11	1
valid_sources[0x53]	13195	1			T1	8		T9	6		T11	1
valid_sources[0x54]	13053	1			T1	1		T9	2		T11	2
valid_sources[0x55]	13405	1			T1	5		T9	6		T11	3
valid_sources[0x56]	14899	1			T1	8		T9	4		T12	13
valid_sources[0x57]	13752	1			T1	1		T11	3		T12	13
valid_sources[0x58]	13479	1			T1	3		T9	3		T11	3
valid_sources[0x59]	14153	1			T1	13		T9	11		T11	2
valid_sources[0x5a]	15323	1			T1	3		T8	1		T9	3
valid_sources[0x5b]	13737	1			T1	9		T9	2		T11	4
valid_sources[0x5c]	19321	1			T1	2		T9	7		T11	4
valid_sources[0x5d]	13553	1			T1	2		T9	4		T11	2
valid_sources[0x5e]	13524	1			T1	2		T9	2		T11	5
valid_sources[0x5f]	18886	1			T1	2		T9	3		T11	1
valid_sources[0x60]	15008	1			T1	7		T9	4		T11	1
valid_sources[0x61]	17326	1			T1	4		T9	1		T11	3
valid_sources[0x62]	13748	1			T1	1		T9	7		T11	4
valid_sources[0x63]	16450	1			T1	8		T9	4		T12	10
valid_sources[0x64]	105230	1			T1	1		T9	11		T11	4
valid_sources[0x65]	13181	1			T1	4		T9	2		T12	11
valid_sources[0x66]	15338	1			T1	5		T3	8		T9	3
valid_sources[0x67]	14433	1			T1	5		T8	1		T9	2
valid_sources[0x68]	13746	1			T1	5		T9	3		T11	6
valid_sources[0x69]	15564	1			T1	3		T9	10		T12	13
valid_sources[0x6a]	13709	1			T1	6		T9	5		T10	1
valid_sources[0x6b]	13171	1			T1	3		T9	2		T11	2
valid_sources[0x6c]	13282	1			T1	6		T9	8		T12	13
valid_sources[0x6d]	13309	1			T1	5		T9	5		T11	2
valid_sources[0x6e]	13387	1			T1	2		T9	6		T11	4
valid_sources[0x6f]	14327	1			T9	3		T12	12		T57	3
valid_sources[0x70]	13507	1			T1	9		T8	1		T9	5
valid_sources[0x71]	13584	1			T1	6		T9	3		T11	4
valid_sources[0x72]	13616	1			T1	1		T9	6		T12	7
valid_sources[0x73]	13657	1			T1	6		T9	4		T11	2
valid_sources[0x74]	13318	1			T1	4		T9	2		T11	3
valid_sources[0x75]	13180	1			T1	9		T9	1		T11	4
valid_sources[0x76]	13333	1			T1	3		T9	2		T11	2
valid_sources[0x77]	13658	1			T1	4		T9	4		T11	1
valid_sources[0x78]	13154	1			T1	7		T9	2		T11	6
valid_sources[0x79]	15820	1			T1	4		T9	2		T11	1
valid_sources[0x7a]	37649	1			T1	3		T9	3		T11	8
valid_sources[0x7b]	14669	1			T1	6		T9	3		T11	4
valid_sources[0x7c]	14728	1			T1	4		T9	2		T11	3
valid_sources[0x7d]	13331	1			T1	3		T9	3		T11	3
valid_sources[0x7e]	13493	1			T1	5		T9	1		T11	2
valid_sources[0x7f]	13665	1			T1	4		T9	3		T11	2
valid_sources[0x80]	37472	1			T1	1		T9	5		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1992903

1

T1

356

T3

24

T9

177

values[0x0]

all_enables

biggest_size

159222

1

T1

70

T3

17

T8

3

values[0x1]

all_enables

biggest_size

157198

1

T1

65

T3

16

T8

3