Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	126144232	15052	0	0
claim_transition_if_regwen_rd_A	126144232	1733	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126144232	15052	0	0
T5	7899	0	0	0
T15	222972	3	0	0
T16	35756	0	0	0
T19	0	2	0	0
T22	1108	0	0	0
T23	30260	0	0	0
T25	38208	0	0	0
T36	0	10	0	0
T38	31699	0	0	0
T57	7955	0	0	0
T58	0	1	0	0
T66	6497	0	0	0
T76	0	1	0	0
T77	17478	0	0	0
T81	0	1	0	0
T146	0	17	0	0
T147	0	18	0	0
T148	0	4	0	0
T149	0	3	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126144232	1733	0	0
T5	7899	0	0	0
T15	222972	16	0	0
T16	35756	0	0	0
T17	0	16	0	0
T19	0	6	0	0
T22	1108	0	0	0
T23	30260	0	0	0
T25	38208	0	0	0
T38	31699	0	0	0
T57	7955	0	0	0
T66	6497	0	0	0
T76	0	17	0	0
T77	17478	0	0	0
T111	0	24	0	0
T112	0	9	0	0
T148	0	5	0	0
T150	0	8	0	0
T151	0	22	0	0
T152	0	22	0	0