Unified Coverage Report :: Module :: prim_flop

Module : prim_flop

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_abstract_flop_0/prim_flop.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_sync_1	75.00			75.00
tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_sync_2	100.00			100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1	100.00			100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2	100.00			100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1	100.00			100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2	100.00			100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1	100.00			100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2	100.00			100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1	100.00			100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2	100.00			100.00
tb.dut.u_prim_flop_2sync_init.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_prim_flop_2sync_init.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_lc_ctrl_kmac_if.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_lc_ctrl_kmac_if.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_lc_ctrl_kmac_if.u_state_regs.u_state_flop
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_lc_ctrl_fsm.u_fsm_state_regs.u_state_flop
tb.dut.u_lc_ctrl_fsm.u_state_regs.u_state_flop
tb.dut.u_lc_ctrl_fsm.u_cnt_regs.u_state_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_raw_test_rma.gen_flops.u_prim_flop.u_secure_anchor_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_dft_en.gen_flops.u_prim_flop.u_secure_anchor_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_nvm_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_cpu_en.gen_flops.u_prim_flop.u_secure_anchor_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_creator_seed_sw_rw_en.gen_flops.u_prim_flop.u_secure_anchor_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_owner_seed_sw_rw_en.gen_flops.u_prim_flop.u_secure_anchor_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_rd_en.gen_flops.u_prim_flop.u_secure_anchor_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_wr_en.gen_flops.u_prim_flop.u_secure_anchor_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_seed_hw_rd_en.gen_flops.u_prim_flop.u_secure_anchor_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_keymgr_en.gen_flops.u_prim_flop.u_secure_anchor_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_escalate_en.gen_flops.u_prim_flop.u_secure_anchor_flop
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_flop_keymgr_div
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_clk_byp_req.gen_flops.u_prim_flop.u_secure_anchor_flop
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_flash_rma_req.gen_flops.u_prim_flop.u_secure_anchor_flop
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_check_byp_en.gen_flops.u_prim_flop.u_secure_anchor_flop
tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	75.00			75.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00			100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00			100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00			100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00			100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00			100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00			100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00			100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00			100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00			100.00

---

Module Instance : tb.dut.u_prim_flop_2sync_init.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_flop_2sync_init.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_kmac_if.u_state_regs.u_state_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_state_regs

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_fsm_state_regs.u_state_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_fsm_state_regs

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_state_regs.u_state_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_state_regs

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_cnt_regs.u_state_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_cnt_regs

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_raw_test_rma.gen_flops.u_prim_flop.u_secure_anchor_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_dft_en.gen_flops.u_prim_flop.u_secure_anchor_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_nvm_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_cpu_en.gen_flops.u_prim_flop.u_secure_anchor_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_creator_seed_sw_rw_en.gen_flops.u_prim_flop.u_secure_anchor_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_owner_seed_sw_rw_en.gen_flops.u_prim_flop.u_secure_anchor_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_rd_en.gen_flops.u_prim_flop.u_secure_anchor_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_wr_en.gen_flops.u_prim_flop.u_secure_anchor_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_seed_hw_rd_en.gen_flops.u_prim_flop.u_secure_anchor_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_keymgr_en.gen_flops.u_prim_flop.u_secure_anchor_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_escalate_en.gen_flops.u_prim_flop.u_secure_anchor_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_flop_keymgr_div

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.69	98.41				91.67	100.00	u_lc_ctrl_signal_decode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_clk_byp_req.gen_flops.u_prim_flop.u_secure_anchor_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_flash_rma_req.gen_flops.u_prim_flop.u_secure_anchor_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_check_byp_en.gen_flops.u_prim_flop.u_secure_anchor_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

Toggle Coverage for Module : prim_flop

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	8	8	100.00
Total Bits 0->1	4	4	100.00
Total Bits 1->0	4	4	100.00

Ports	4	4	100.00
Port Bits	8	8	100.00
Port Bits 0->1	4	4	100.00
Port Bits 1->0	4	4	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
d_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
q_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_sync_1

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	8	6	75.00
Total Bits 0->1	4	3	75.00
Total Bits 1->0	4	3	75.00

Ports	4	3	75.00
Port Bits	8	6	75.00
Port Bits 0->1	4	3	75.00
Port Bits 1->0	4	3	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
d_i	No	No		No		INPUT
q_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_sync_2

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	8	8	100.00
Total Bits 0->1	4	4	100.00
Total Bits 1->0	4	4	100.00

Ports	4	4	100.00
Port Bits	8	8	100.00
Port Bits 0->1	4	4	100.00
Port Bits 1->0	4	4	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
d_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
q_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	8	8	100.00
Total Bits 0->1	4	4	100.00
Total Bits 1->0	4	4	100.00

Ports	4	4	100.00
Port Bits	8	8	100.00
Port Bits 0->1	4	4	100.00
Port Bits 1->0	4	4	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
d_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
q_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	8	8	100.00
Total Bits 0->1	4	4	100.00
Total Bits 1->0	4	4	100.00

Ports	4	4	100.00
Port Bits	8	8	100.00
Port Bits 0->1	4	4	100.00
Port Bits 1->0	4	4	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
d_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
q_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	8	8	100.00
Total Bits 0->1	4	4	100.00
Total Bits 1->0	4	4	100.00

Ports	4	4	100.00
Port Bits	8	8	100.00
Port Bits 0->1	4	4	100.00
Port Bits 1->0	4	4	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
d_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
q_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	8	8	100.00
Total Bits 0->1	4	4	100.00
Total Bits 1->0	4	4	100.00

Ports	4	4	100.00
Port Bits	8	8	100.00
Port Bits 0->1	4	4	100.00
Port Bits 1->0	4	4	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
d_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
q_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	8	8	100.00
Total Bits 0->1	4	4	100.00
Total Bits 1->0	4	4	100.00

Ports	4	4	100.00
Port Bits	8	8	100.00
Port Bits 0->1	4	4	100.00
Port Bits 1->0	4	4	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
d_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
q_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	8	8	100.00
Total Bits 0->1	4	4	100.00
Total Bits 1->0	4	4	100.00

Ports	4	4	100.00
Port Bits	8	8	100.00
Port Bits 0->1	4	4	100.00
Port Bits 1->0	4	4	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
d_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
q_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	8	8	100.00
Total Bits 0->1	4	4	100.00
Total Bits 1->0	4	4	100.00

Ports	4	4	100.00
Port Bits	8	8	100.00
Port Bits 0->1	4	4	100.00
Port Bits 1->0	4	4	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
d_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
q_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	8	8	100.00
Total Bits 0->1	4	4	100.00
Total Bits 1->0	4	4	100.00

Ports	4	4	100.00
Port Bits	8	8	100.00
Port Bits 0->1	4	4	100.00
Port Bits 1->0	4	4	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
d_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
q_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT