Unified Coverage Report :: Module :: prim_generic_flop_2sync

Module : prim_generic_flop_2sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_2sync_0/rtl/prim_generic_flop_2sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic	100.00			100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic	100.00			100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic	100.00			100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic	100.00			100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic	100.00			100.00
tb.dut.u_prim_flop_2sync_init.gen_generic.u_impl_generic
tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic
tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic
tb.dut.u_lc_ctrl_kmac_if.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.91			90.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				u_combined_rstn_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_cdc_rand_delay	100.00			100.00
u_sync_1	75.00			75.00
u_sync_2	100.00			100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				gen_rz_hs_protocol.ack_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_cdc_rand_delay	100.00			100.00
u_sync_1	100.00			100.00
u_sync_2	100.00			100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				gen_rz_hs_protocol.req_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_cdc_rand_delay	100.00			100.00
u_sync_1	100.00			100.00
u_sync_2	100.00			100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				gen_rz_hs_protocol.ack_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_cdc_rand_delay	100.00			100.00
u_sync_1	100.00			100.00
u_sync_2	100.00			100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				gen_rz_hs_protocol.req_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_cdc_rand_delay	100.00			100.00
u_sync_1	100.00			100.00
u_sync_2	100.00			100.00

---

Module Instance : tb.dut.u_prim_flop_2sync_init.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_flop_2sync_init

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_nrz_hs_protocol.req_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_nrz_hs_protocol.ack_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_flop_2sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop_2sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop_2sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop_2sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00

Toggle Coverage for Module : prim_generic_flop_2sync

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	8	8	100.00
Total Bits 0->1	4	4	100.00
Total Bits 1->0	4	4	100.00

Ports	4	4	100.00
Port Bits	8	8	100.00
Port Bits 0->1	4	4	100.00
Port Bits 1->0	4	4	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
d_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
q_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic

	Total	Covered	Percent
Totals	3	3	100.00
Total Bits	6	6	100.00
Total Bits 0->1	3	3	100.00
Total Bits 1->0	3	3	100.00

Ports	3	3	100.00
Port Bits	6	6	100.00
Port Bits 0->1	3	3	100.00
Port Bits 1->0	3	3	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
d_i	Unreachable	Unreachable		Unreachable		INPUT
q_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	8	8	100.00
Total Bits 0->1	4	4	100.00
Total Bits 1->0	4	4	100.00

Ports	4	4	100.00
Port Bits	8	8	100.00
Port Bits 0->1	4	4	100.00
Port Bits 1->0	4	4	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
d_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
q_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	8	8	100.00
Total Bits 0->1	4	4	100.00
Total Bits 1->0	4	4	100.00

Ports	4	4	100.00
Port Bits	8	8	100.00
Port Bits 0->1	4	4	100.00
Port Bits 1->0	4	4	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
d_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
q_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	8	8	100.00
Total Bits 0->1	4	4	100.00
Total Bits 1->0	4	4	100.00

Ports	4	4	100.00
Port Bits	8	8	100.00
Port Bits 0->1	4	4	100.00
Port Bits 1->0	4	4	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
d_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
q_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	8	8	100.00
Total Bits 0->1	4	4	100.00
Total Bits 1->0	4	4	100.00

Ports	4	4	100.00
Port Bits	8	8	100.00
Port Bits 0->1	4	4	100.00
Port Bits 1->0	4	4	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
d_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
q_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT