Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	112700720	15986	0	0
claim_transition_if_regwen_rd_A	112700720	1295	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112700720	15986	0	0
T6	4126	0	0	0
T17	846674	9	0	0
T18	229221	0	0	0
T19	20520	0	0	0
T20	29529	0	0	0
T21	36604	0	0	0
T22	0	6	0	0
T42	0	2	0	0
T45	31620	0	0	0
T63	0	3	0	0
T66	0	11	0	0
T77	0	9	0	0
T91	4209	0	0	0
T93	1360	0	0	0
T96	23640	0	0	0
T97	0	18	0	0
T144	0	1	0	0
T145	0	2	0	0
T146	0	7	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112700720	1295	0	0
T22	599149	1	0	0
T46	26540	0	0	0
T48	28226	0	0	0
T55	42202	0	0	0
T58	29108	0	0	0
T67	648004	0	0	0
T95	0	15	0	0
T109	0	10	0	0
T118	0	18	0	0
T147	0	8	0	0
T148	0	11	0	0
T149	0	12	0	0
T150	0	265	0	0
T151	0	6	0	0
T152	0	17	0	0
T153	31281	0	0	0
T154	1975	0	0	0
T155	243369	0	0	0
T156	2649	0	0	0