Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2146950	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2370594

1

T1

84

T3

329

T11

228

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4164649	1			T1	95		T3	272		T11	173
values[0x0]	175884	1			T1	35		T3	100		T11	67
values[0x1]	177011	1			T1	19		T3	92		T11	93

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1707061	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2810483

1

T1

94

T3

365

T11

253

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15224	1			T3	1		T12	2		T13	10
valid_sources[0x01]	14013	1			T1	1		T3	1		T13	2
valid_sources[0x02]	76599	1			T1	1		T3	7		T12	1
valid_sources[0x03]	13901	1			T3	3		T14	5		T15	1
valid_sources[0x04]	14154	1			T1	2		T3	1		T12	1
valid_sources[0x05]	14245	1			T1	2		T3	2		T13	9
valid_sources[0x06]	14342	1			T1	2		T3	1		T13	4
valid_sources[0x07]	14277	1			T1	1		T3	1		T13	12
valid_sources[0x08]	14075	1			T3	1		T13	3		T14	25
valid_sources[0x09]	24139	1			T12	1		T13	6		T14	2
valid_sources[0x0a]	14526	1			T13	8		T14	1		T15	1
valid_sources[0x0b]	13903	1			T3	5		T13	2		T14	1
valid_sources[0x0c]	14335	1			T3	2		T12	4		T13	3
valid_sources[0x0d]	15811	1			T1	3		T13	6		T14	2
valid_sources[0x0e]	14204	1			T12	1		T13	10		T14	2
valid_sources[0x0f]	16595	1			T1	3		T3	1		T13	16
valid_sources[0x10]	14508	1			T3	3		T12	1		T13	5
valid_sources[0x11]	13793	1			T12	1		T13	10		T14	6
valid_sources[0x12]	14385	1			T13	4		T15	5		T57	12
valid_sources[0x13]	29343	1			T1	3		T3	2		T12	1
valid_sources[0x14]	34497	1			T3	3		T13	3		T14	12
valid_sources[0x15]	15633	1			T1	2		T12	1		T13	4
valid_sources[0x16]	14070	1			T13	3		T14	5		T15	7
valid_sources[0x17]	14019	1			T3	6		T12	1		T13	5
valid_sources[0x18]	14508	1			T1	1		T3	2		T13	1
valid_sources[0x19]	18113	1			T1	1		T3	2		T13	4
valid_sources[0x1a]	13810	1			T1	1		T3	2		T13	11
valid_sources[0x1b]	14407	1			T3	2		T12	6		T13	5
valid_sources[0x1c]	13945	1			T3	2		T13	6		T14	7
valid_sources[0x1d]	14046	1			T12	1		T13	12		T14	3
valid_sources[0x1e]	14033	1			T3	1		T12	2		T13	5
valid_sources[0x1f]	15612	1			T1	1		T3	2		T13	2
valid_sources[0x20]	15325	1			T3	2		T13	3		T14	3
valid_sources[0x21]	14291	1			T3	4		T14	4		T15	2
valid_sources[0x22]	13880	1			T3	2		T13	5		T14	4
valid_sources[0x23]	15821	1			T3	2		T12	1		T13	8
valid_sources[0x24]	14207	1			T1	3		T3	3		T12	1
valid_sources[0x25]	14212	1			T3	1		T12	1		T13	9
valid_sources[0x26]	15899	1			T1	1		T3	2		T13	13
valid_sources[0x27]	14303	1			T13	5		T14	9		T15	1
valid_sources[0x28]	14627	1			T1	2		T3	2		T13	6
valid_sources[0x29]	14722	1			T3	1		T13	9		T14	4
valid_sources[0x2a]	14133	1			T1	1		T3	4		T14	4
valid_sources[0x2b]	14631	1			T3	5		T13	10		T14	4
valid_sources[0x2c]	13988	1			T1	4		T3	2		T13	17
valid_sources[0x2d]	16716	1			T1	1		T12	2		T13	9
valid_sources[0x2e]	14292	1			T1	2		T3	11		T12	3
valid_sources[0x2f]	14064	1			T1	1		T3	2		T12	1
valid_sources[0x30]	14119	1			T1	1		T15	1		T23	17
valid_sources[0x31]	15614	1			T1	1		T3	2		T13	13
valid_sources[0x32]	14321	1			T13	4		T14	9		T15	1
valid_sources[0x33]	15790	1			T11	333		T12	2		T14	1
valid_sources[0x34]	14507	1			T1	1		T13	7		T14	2
valid_sources[0x35]	34288	1			T3	1		T13	4		T14	11
valid_sources[0x36]	15039	1			T1	2		T3	1		T13	2
valid_sources[0x37]	14011	1			T3	1		T12	1		T13	12
valid_sources[0x38]	15232	1			T3	3		T13	8		T14	2
valid_sources[0x39]	13968	1			T3	3		T12	3		T13	6
valid_sources[0x3a]	14556	1			T3	1		T13	7		T15	5
valid_sources[0x3b]	13834	1			T13	2		T14	13		T15	1
valid_sources[0x3c]	14149	1			T3	2		T12	1		T13	1
valid_sources[0x3d]	14089	1			T3	2		T12	1		T13	8
valid_sources[0x3e]	19889	1			T3	4		T13	3		T14	3
valid_sources[0x3f]	14184	1			T1	2		T13	8		T14	10
valid_sources[0x40]	13792	1			T1	1		T3	1		T12	6
valid_sources[0x41]	13766	1			T1	1		T3	3		T12	5
valid_sources[0x42]	14297	1			T1	1		T3	3		T13	13
valid_sources[0x43]	14640	1			T13	2		T14	6		T15	1
valid_sources[0x44]	16124	1			T3	2		T13	5		T14	3
valid_sources[0x45]	13870	1			T1	2		T12	1		T13	2
valid_sources[0x46]	14273	1			T1	2		T12	1		T13	16
valid_sources[0x47]	15239	1			T3	9		T13	11		T14	16
valid_sources[0x48]	21093	1			T3	1		T13	11		T14	14
valid_sources[0x49]	13950	1			T13	10		T14	8		T23	58
valid_sources[0x4a]	16555	1			T13	7		T14	13		T15	5
valid_sources[0x4b]	17370	1			T1	2		T3	2		T14	6
valid_sources[0x4c]	16491	1			T3	4		T12	2		T13	1
valid_sources[0x4d]	14344	1			T3	5		T13	16		T14	14
valid_sources[0x4e]	14392	1			T3	1		T13	4		T14	8
valid_sources[0x4f]	13946	1			T13	4		T14	5		T15	1
valid_sources[0x50]	17227	1			T3	6		T12	1		T13	4
valid_sources[0x51]	14541	1			T3	5		T12	4		T13	12
valid_sources[0x52]	14509	1			T1	1		T3	2		T13	12
valid_sources[0x53]	14053	1			T3	2		T13	10		T14	2
valid_sources[0x54]	14476	1			T1	1		T3	1		T12	1
valid_sources[0x55]	13907	1			T1	1		T3	2		T12	4
valid_sources[0x56]	14305	1			T1	1		T3	3		T12	2
valid_sources[0x57]	14262	1			T3	3		T13	10		T14	4
valid_sources[0x58]	13709	1			T1	1		T3	2		T13	4
valid_sources[0x59]	14102	1			T3	2		T12	2		T13	5
valid_sources[0x5a]	14493	1			T1	3		T12	2		T13	10
valid_sources[0x5b]	15320	1			T1	1		T3	1		T13	12
valid_sources[0x5c]	14630	1			T3	3		T13	7		T14	7
valid_sources[0x5d]	16050	1			T3	4		T13	2		T14	4
valid_sources[0x5e]	14541	1			T3	5		T13	13		T14	6
valid_sources[0x5f]	13826	1			T1	2		T3	3		T13	7
valid_sources[0x60]	14677	1			T3	1		T13	14		T14	3
valid_sources[0x61]	46167	1			T1	1		T3	3		T13	7
valid_sources[0x62]	13954	1			T12	3		T13	1		T14	9
valid_sources[0x63]	14182	1			T1	2		T3	3		T12	2
valid_sources[0x64]	44111	1			T1	1		T3	1		T13	6
valid_sources[0x65]	13920	1			T1	1		T3	1		T13	9
valid_sources[0x66]	14317	1			T1	1		T3	1		T12	4
valid_sources[0x67]	23757	1			T1	1		T3	2		T13	7
valid_sources[0x68]	14230	1			T1	1		T3	1		T13	4
valid_sources[0x69]	14485	1			T3	9		T12	1		T13	5
valid_sources[0x6a]	17030	1			T1	1		T3	5		T13	6
valid_sources[0x6b]	15836	1			T13	3		T14	2		T15	2
valid_sources[0x6c]	14073	1			T1	1		T3	1		T13	5
valid_sources[0x6d]	14308	1			T3	1		T13	2		T14	1
valid_sources[0x6e]	55220	1			T3	1		T12	2		T13	7
valid_sources[0x6f]	18903	1			T13	5		T14	12		T15	4
valid_sources[0x70]	14145	1			T1	2		T3	2		T13	14
valid_sources[0x71]	16021	1			T3	2		T12	2		T13	14
valid_sources[0x72]	14481	1			T13	10		T14	3		T15	2
valid_sources[0x73]	14225	1			T12	2		T13	3		T14	7
valid_sources[0x74]	49564	1			T1	1		T3	1		T12	3
valid_sources[0x75]	14455	1			T13	20		T14	4		T15	1
valid_sources[0x76]	13664	1			T1	1		T13	1		T14	1
valid_sources[0x77]	13797	1			T3	1		T12	3		T13	10
valid_sources[0x78]	14633	1			T1	1		T13	6		T14	9
valid_sources[0x79]	13838	1			T1	1		T13	8		T14	6
valid_sources[0x7a]	14541	1			T1	1		T12	1		T13	5
valid_sources[0x7b]	14370	1			T1	1		T3	5		T13	8
valid_sources[0x7c]	14271	1			T13	18		T14	6		T15	7
valid_sources[0x7d]	15632	1			T3	3		T13	4		T14	6
valid_sources[0x7e]	14144	1			T1	1		T13	3		T14	10
valid_sources[0x7f]	14956	1			T1	1		T13	4		T14	3
valid_sources[0x80]	14135	1			T1	3		T3	2		T12	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2066187

1

T1

41

T3

164

T11

89

values[0x0]

all_enables

biggest_size

152649

1

T1

27

T3

90

T11

56

values[0x1]

all_enables

biggest_size

151758

1

T1

16

T3

75

T11

83