Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1635274	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1854861

1

T1

413

T2

39

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3150266	1			T1	415		T2	46		T3	4
values[0x0]	169659	1			T1	167		T2	7		T3	2
values[0x1]	170210	1			T1	161		T2	9		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1300053	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2190082

1

T1

493

T2

42

T3

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11959	1			T4	3		T12	8		T21	7
valid_sources[0x01]	12463	1			T1	6		T4	6		T12	13
valid_sources[0x02]	18335	1			T1	9		T4	6		T12	8
valid_sources[0x03]	13067	1			T1	3		T4	2		T12	6
valid_sources[0x04]	12182	1			T1	5		T4	4		T12	9
valid_sources[0x05]	12846	1			T1	1		T4	5		T12	1
valid_sources[0x06]	12145	1			T1	3		T2	1		T4	2
valid_sources[0x07]	11901	1			T1	2		T12	7		T21	7
valid_sources[0x08]	11994	1			T4	4		T12	7		T9	1
valid_sources[0x09]	12206	1			T1	1		T2	4		T4	8
valid_sources[0x0a]	12103	1			T1	2		T4	6		T12	10
valid_sources[0x0b]	13035	1			T1	1		T2	3		T4	3
valid_sources[0x0c]	13426	1			T1	2		T4	4		T12	3
valid_sources[0x0d]	12692	1			T1	5		T4	4		T12	8
valid_sources[0x0e]	12147	1			T1	6		T2	2		T4	4
valid_sources[0x0f]	11847	1			T1	3		T4	4		T12	7
valid_sources[0x10]	12841	1			T1	1		T4	8		T12	7
valid_sources[0x11]	13584	1			T1	3		T4	5		T12	8
valid_sources[0x12]	11980	1			T1	2		T4	3		T12	5
valid_sources[0x13]	12804	1			T1	5		T4	4		T12	5
valid_sources[0x14]	12614	1			T4	8		T12	6		T27	3
valid_sources[0x15]	12190	1			T1	1		T4	11		T12	8
valid_sources[0x16]	12203	1			T1	3		T2	1		T4	11
valid_sources[0x17]	13162	1			T1	3		T4	5		T12	8
valid_sources[0x18]	12328	1			T1	2		T4	7		T12	3
valid_sources[0x19]	11875	1			T1	2		T4	3		T12	6
valid_sources[0x1a]	12692	1			T1	4		T4	4		T12	4
valid_sources[0x1b]	13326	1			T1	1		T4	4		T12	5
valid_sources[0x1c]	15696	1			T1	6		T4	1		T12	7
valid_sources[0x1d]	12538	1			T1	4		T4	5		T12	1
valid_sources[0x1e]	12433	1			T1	3		T4	2		T12	8
valid_sources[0x1f]	12122	1			T1	1		T4	5		T12	4
valid_sources[0x20]	12283	1			T1	1		T4	2		T12	9
valid_sources[0x21]	12051	1			T1	1		T4	3		T12	3
valid_sources[0x22]	12200	1			T1	4		T4	4		T12	3
valid_sources[0x23]	12069	1			T1	3		T4	7		T12	9
valid_sources[0x24]	63657	1			T1	1		T4	7		T12	7
valid_sources[0x25]	12077	1			T1	1		T2	2		T4	4
valid_sources[0x26]	15865	1			T1	2		T4	5		T12	9
valid_sources[0x27]	12236	1			T1	4		T4	9		T12	5
valid_sources[0x28]	12411	1			T1	4		T4	8		T12	5
valid_sources[0x29]	12370	1			T1	4		T4	2		T12	12
valid_sources[0x2a]	12163	1			T1	3		T4	2		T12	3
valid_sources[0x2b]	13884	1			T1	4		T4	3		T12	5
valid_sources[0x2c]	12293	1			T1	4		T4	8		T12	3
valid_sources[0x2d]	12479	1			T1	3		T4	6		T12	8
valid_sources[0x2e]	11850	1			T1	2		T4	8		T12	12
valid_sources[0x2f]	13637	1			T1	1		T4	1		T12	6
valid_sources[0x30]	16168	1			T1	1		T4	7		T12	16
valid_sources[0x31]	12076	1			T1	3		T4	3		T12	7
valid_sources[0x32]	11989	1			T1	3		T4	1		T12	4
valid_sources[0x33]	11976	1			T1	2		T4	3		T12	5
valid_sources[0x34]	12170	1			T1	5		T4	6		T12	5
valid_sources[0x35]	12304	1			T1	5		T4	3		T12	6
valid_sources[0x36]	12505	1			T1	5		T4	2		T12	5
valid_sources[0x37]	21465	1			T1	1		T4	1		T12	7
valid_sources[0x38]	12007	1			T1	3		T4	5		T12	7
valid_sources[0x39]	12114	1			T1	2		T2	2		T4	3
valid_sources[0x3a]	12053	1			T4	3		T12	10		T21	4
valid_sources[0x3b]	12103	1			T4	5		T12	12		T21	15
valid_sources[0x3c]	12016	1			T1	1		T4	5		T12	8
valid_sources[0x3d]	12341	1			T1	2		T4	3		T12	10
valid_sources[0x3e]	16543	1			T1	4		T4	4		T12	1
valid_sources[0x3f]	12065	1			T1	6		T4	3		T12	3
valid_sources[0x40]	12376	1			T1	6		T4	7		T12	12
valid_sources[0x41]	12048	1			T1	4		T4	6		T12	13
valid_sources[0x42]	13819	1			T4	1		T12	9		T21	9
valid_sources[0x43]	12173	1			T1	1		T4	10		T12	2
valid_sources[0x44]	13419	1			T4	3		T12	12		T21	8
valid_sources[0x45]	12287	1			T1	5		T4	4		T12	4
valid_sources[0x46]	13156	1			T1	5		T2	3		T4	3
valid_sources[0x47]	12001	1			T1	5		T2	1		T4	4
valid_sources[0x48]	13034	1			T1	4		T4	6		T12	4
valid_sources[0x49]	11489	1			T1	2		T4	3		T12	5
valid_sources[0x4a]	11802	1			T1	1		T4	1		T21	3
valid_sources[0x4b]	12362	1			T1	4		T4	4		T12	5
valid_sources[0x4c]	13181	1			T1	2		T4	1		T12	8
valid_sources[0x4d]	11944	1			T1	1		T4	7		T12	7
valid_sources[0x4e]	13966	1			T1	3		T4	3		T12	7
valid_sources[0x4f]	13987	1			T1	5		T4	8		T12	4
valid_sources[0x50]	13001	1			T4	2		T12	7		T21	3
valid_sources[0x51]	12204	1			T1	1		T2	1		T4	8
valid_sources[0x52]	12200	1			T1	6		T4	5		T12	7
valid_sources[0x53]	12757	1			T1	2		T2	2		T4	6
valid_sources[0x54]	11843	1			T1	2		T4	1		T12	13
valid_sources[0x55]	12540	1			T1	4		T4	3		T12	12
valid_sources[0x56]	32977	1			T1	5		T2	3		T4	3
valid_sources[0x57]	39705	1			T1	2		T2	1		T4	7
valid_sources[0x58]	12169	1			T1	3		T4	1		T12	4
valid_sources[0x59]	12708	1			T1	4		T4	4		T12	3
valid_sources[0x5a]	11827	1			T1	2		T4	7		T12	3
valid_sources[0x5b]	13370	1			T1	3		T4	5		T12	5
valid_sources[0x5c]	13307	1			T1	11		T4	9		T12	4
valid_sources[0x5d]	11718	1			T1	3		T2	1		T4	4
valid_sources[0x5e]	14352	1			T1	3		T4	7		T12	7
valid_sources[0x5f]	12041	1			T1	1		T4	4		T12	7
valid_sources[0x60]	13214	1			T1	1		T4	9		T12	6
valid_sources[0x61]	12051	1			T1	1		T4	5		T12	9
valid_sources[0x62]	12170	1			T1	1		T2	3		T4	5
valid_sources[0x63]	11986	1			T1	1		T4	3		T12	1
valid_sources[0x64]	12259	1			T1	1		T4	4		T12	6
valid_sources[0x65]	17467	1			T1	5		T4	3		T12	6
valid_sources[0x66]	12716	1			T1	1		T4	4		T12	3
valid_sources[0x67]	12243	1			T1	7		T4	13		T12	1
valid_sources[0x68]	12012	1			T4	6		T12	3		T21	6
valid_sources[0x69]	13313	1			T1	3		T4	5		T12	9
valid_sources[0x6a]	15303	1			T4	5		T12	4		T21	8
valid_sources[0x6b]	12167	1			T1	2		T4	6		T12	9
valid_sources[0x6c]	12168	1			T1	8		T4	3		T12	8
valid_sources[0x6d]	12104	1			T1	2		T4	7		T12	8
valid_sources[0x6e]	11923	1			T4	2		T12	5		T21	2
valid_sources[0x6f]	12206	1			T1	1		T4	4		T12	2
valid_sources[0x70]	14003	1			T1	1		T4	4		T12	13
valid_sources[0x71]	12984	1			T1	3		T4	3		T12	3
valid_sources[0x72]	14345	1			T4	5		T12	1		T21	4
valid_sources[0x73]	12478	1			T1	3		T4	4		T12	2
valid_sources[0x74]	12113	1			T1	5		T4	2		T12	3
valid_sources[0x75]	12198	1			T1	8		T4	4		T12	7
valid_sources[0x76]	11923	1			T1	4		T2	2		T4	3
valid_sources[0x77]	12323	1			T4	2		T12	5		T21	7
valid_sources[0x78]	15922	1			T1	1		T2	1		T4	2
valid_sources[0x79]	14652	1			T1	4		T4	4		T12	6
valid_sources[0x7a]	12373	1			T1	2		T4	7		T12	6
valid_sources[0x7b]	11958	1			T1	5		T4	7		T12	2
valid_sources[0x7c]	12673	1			T1	1		T4	3		T12	6
valid_sources[0x7d]	14850	1			T2	1		T4	3		T12	5
valid_sources[0x7e]	12568	1			T1	5		T2	5		T4	4
valid_sources[0x7f]	11899	1			T1	3		T4	4		T12	8
valid_sources[0x80]	13186	1			T1	8		T2	2		T4	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1561170

1

T1

138

T2

26

T4

331

values[0x0]

all_enables

biggest_size

147407

1

T1

139

T2

5

T3

2

values[0x1]

all_enables

biggest_size

146284

1

T1

136

T2

8

T3

3