Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	106762273	14948	0	0
claim_transition_if_regwen_rd_A	106762273	1735	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106762273	14948	0	0
T11	30023	0	0	0
T46	151376	1	0	0
T56	19510	0	0	0
T58	0	7	0	0
T63	3104	0	0	0
T90	0	4	0	0
T92	0	10	0	0
T143	0	2	0	0
T146	0	4	0	0
T147	0	3	0	0
T148	0	2	0	0
T149	0	5	0	0
T150	0	1	0	0
T151	1599	0	0	0
T152	9005	0	0	0
T153	50484	0	0	0
T154	20810	0	0	0
T155	79875	0	0	0
T156	8169	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106762273	1735	0	0
T34	22927	0	0	0
T110	0	69	0	0
T136	0	47	0	0
T143	131313	2	0	0
T157	0	5	0	0
T158	0	1	0	0
T159	0	5	0	0
T160	0	8	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	2	0	0
T164	923	0	0	0
T165	11729	0	0	0
T166	17410	0	0	0
T167	17695	0	0	0
T168	35724	0	0	0
T169	8726	0	0	0
T170	95038	0	0	0
T171	25177	0	0	0