Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1280805	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1485152

1

T1

8207

T3

706

T9

888

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2439451	1			T1	13973		T3	512		T9	567
values[0x0]	162883	1			T1	773		T3	252		T9	372
values[0x1]	163623	1			T1	783		T3	284		T9	396

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1015664	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1750293

1

T1

9758

T3

795

T9

1002

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10286	1			T3	7		T9	7		T10	7
valid_sources[0x01]	8277	1			T3	6		T9	1		T10	4
valid_sources[0x02]	8498	1			T1	17		T3	5		T9	7
valid_sources[0x03]	8430	1			T1	17		T3	3		T9	4
valid_sources[0x04]	9110	1			T3	4		T9	4		T10	5
valid_sources[0x05]	8416	1			T3	5		T9	7		T10	4
valid_sources[0x06]	20519	1			T1	12206		T3	5		T9	3
valid_sources[0x07]	10796	1			T3	3		T9	8		T10	4
valid_sources[0x08]	8351	1			T1	17		T3	6		T9	4
valid_sources[0x09]	9090	1			T3	8		T9	7		T10	1
valid_sources[0x0a]	8272	1			T1	17		T3	3		T9	5
valid_sources[0x0b]	36010	1			T3	3		T9	2		T10	7
valid_sources[0x0c]	9683	1			T3	5		T9	5		T10	9
valid_sources[0x0d]	8521	1			T3	3		T9	11		T10	6
valid_sources[0x0e]	8741	1			T3	6		T9	5		T10	4
valid_sources[0x0f]	8096	1			T3	3		T9	9		T10	7
valid_sources[0x10]	8383	1			T3	2		T9	4		T10	8
valid_sources[0x11]	13367	1			T3	3		T10	6		T11	4
valid_sources[0x12]	8423	1			T3	5		T9	4		T10	3
valid_sources[0x13]	14566	1			T3	7		T9	4		T10	11
valid_sources[0x14]	8257	1			T3	3		T9	5		T10	5
valid_sources[0x15]	8501	1			T3	5		T9	2		T10	4
valid_sources[0x16]	9063	1			T3	5		T9	7		T10	3
valid_sources[0x17]	11633	1			T3	5		T9	5		T10	8
valid_sources[0x18]	11358	1			T3	4		T9	5		T10	6
valid_sources[0x19]	10380	1			T3	4		T9	6		T10	5
valid_sources[0x1a]	8414	1			T3	6		T9	3		T10	7
valid_sources[0x1b]	8271	1			T9	4		T10	2		T4	584
valid_sources[0x1c]	12822	1			T3	1		T9	9		T10	8
valid_sources[0x1d]	9547	1			T3	4		T9	2		T10	10
valid_sources[0x1e]	10099	1			T3	4		T9	6		T10	3
valid_sources[0x1f]	8302	1			T3	4		T9	9		T10	7
valid_sources[0x20]	9118	1			T3	5		T9	8		T10	3
valid_sources[0x21]	8247	1			T3	2		T9	4		T10	11
valid_sources[0x22]	11839	1			T3	4		T9	4		T10	3
valid_sources[0x23]	11824	1			T1	1		T3	6		T9	7
valid_sources[0x24]	8406	1			T3	6		T9	3		T10	8
valid_sources[0x25]	8734	1			T3	5		T9	5		T10	5
valid_sources[0x26]	8257	1			T3	2		T9	4		T10	2
valid_sources[0x27]	10252	1			T3	2		T9	6		T10	2
valid_sources[0x28]	8201	1			T9	9		T10	6		T11	2
valid_sources[0x29]	8327	1			T3	3		T9	3		T10	6
valid_sources[0x2a]	9673	1			T3	3		T9	3		T10	10
valid_sources[0x2b]	8088	1			T3	4		T9	5		T10	8
valid_sources[0x2c]	8385	1			T3	6		T9	6		T10	11
valid_sources[0x2d]	8484	1			T3	2		T9	5		T10	5
valid_sources[0x2e]	9740	1			T1	17		T3	5		T9	3
valid_sources[0x2f]	8450	1			T3	3		T9	9		T10	3
valid_sources[0x30]	10088	1			T3	4		T9	3		T10	8
valid_sources[0x31]	8451	1			T3	4		T9	9		T10	7
valid_sources[0x32]	9783	1			T3	3		T9	4		T10	4
valid_sources[0x33]	9885	1			T3	5		T9	7		T10	4
valid_sources[0x34]	9678	1			T3	2		T9	7		T10	3
valid_sources[0x35]	8284	1			T3	5		T9	9		T10	6
valid_sources[0x36]	8933	1			T3	3		T9	4		T10	5
valid_sources[0x37]	9602	1			T3	5		T9	7		T10	6
valid_sources[0x38]	13242	1			T3	3		T9	1		T10	3
valid_sources[0x39]	12315	1			T3	5		T9	9		T10	4
valid_sources[0x3a]	9928	1			T3	3		T9	1		T10	6
valid_sources[0x3b]	10884	1			T3	4		T9	1		T10	7
valid_sources[0x3c]	8008	1			T3	5		T9	5		T10	8
valid_sources[0x3d]	8153	1			T9	11		T10	8		T4	542
valid_sources[0x3e]	9079	1			T3	6		T9	10		T10	9
valid_sources[0x3f]	10165	1			T3	3		T9	8		T10	7
valid_sources[0x40]	8276	1			T3	2		T9	1		T10	3
valid_sources[0x41]	8407	1			T3	6		T9	3		T10	2
valid_sources[0x42]	8738	1			T3	3		T9	6		T10	10
valid_sources[0x43]	8338	1			T3	2		T9	5		T10	8
valid_sources[0x44]	8880	1			T3	8		T9	4		T10	3
valid_sources[0x45]	10111	1			T3	3		T10	6		T11	3
valid_sources[0x46]	8517	1			T3	7		T9	7		T10	4
valid_sources[0x47]	8433	1			T3	3		T9	2		T10	4
valid_sources[0x48]	8802	1			T3	4		T10	8		T11	3
valid_sources[0x49]	8552	1			T3	3		T9	7		T10	3
valid_sources[0x4a]	8433	1			T3	4		T9	10		T10	5
valid_sources[0x4b]	8223	1			T3	5		T9	7		T10	7
valid_sources[0x4c]	10012	1			T3	3		T9	9		T10	7
valid_sources[0x4d]	8429	1			T3	4		T9	7		T10	2
valid_sources[0x4e]	8418	1			T3	3		T9	3		T10	11
valid_sources[0x4f]	9746	1			T3	8		T9	2		T10	3
valid_sources[0x50]	7904	1			T3	7		T9	4		T10	10
valid_sources[0x51]	10866	1			T3	2		T9	6		T10	13
valid_sources[0x52]	11194	1			T1	17		T3	4		T9	5
valid_sources[0x53]	41182	1			T3	5		T9	2		T10	4
valid_sources[0x54]	8732	1			T3	7		T9	6		T10	11
valid_sources[0x55]	8634	1			T1	17		T3	3		T9	6
valid_sources[0x56]	9899	1			T1	17		T3	4		T9	6
valid_sources[0x57]	9740	1			T3	1		T9	6		T10	5
valid_sources[0x58]	12719	1			T3	2		T9	9		T10	4
valid_sources[0x59]	8666	1			T1	17		T3	5		T9	6
valid_sources[0x5a]	8289	1			T3	6		T9	10		T10	7
valid_sources[0x5b]	9605	1			T3	1		T9	4		T10	8
valid_sources[0x5c]	8421	1			T3	3		T9	5		T10	8
valid_sources[0x5d]	8233	1			T1	17		T3	5		T9	8
valid_sources[0x5e]	10625	1			T3	6		T9	6		T10	4
valid_sources[0x5f]	8048	1			T3	2		T9	5		T10	6
valid_sources[0x60]	11208	1			T3	3		T9	4		T10	9
valid_sources[0x61]	8278	1			T3	6		T9	12		T10	3
valid_sources[0x62]	10063	1			T3	7		T9	5		T10	5
valid_sources[0x63]	8417	1			T3	11		T9	3		T10	11
valid_sources[0x64]	8386	1			T3	2		T9	8		T10	7
valid_sources[0x65]	9312	1			T3	4		T9	7		T11	4
valid_sources[0x66]	10008	1			T3	2		T9	2		T10	2
valid_sources[0x67]	8319	1			T3	6		T9	9		T10	4
valid_sources[0x68]	8302	1			T3	1		T9	4		T10	5
valid_sources[0x69]	8438	1			T3	3		T10	5		T4	565
valid_sources[0x6a]	8085	1			T3	4		T9	7		T10	2
valid_sources[0x6b]	12402	1			T3	3		T9	4		T10	4
valid_sources[0x6c]	8487	1			T3	9		T9	6		T10	5
valid_sources[0x6d]	8448	1			T3	11		T9	6		T10	3
valid_sources[0x6e]	8401	1			T3	2		T9	1		T10	7
valid_sources[0x6f]	10052	1			T3	10		T9	4		T10	6
valid_sources[0x70]	8280	1			T3	5		T9	4		T10	11
valid_sources[0x71]	8536	1			T3	4		T9	4		T10	6
valid_sources[0x72]	8638	1			T3	3		T9	5		T10	7
valid_sources[0x73]	8182	1			T3	1		T9	6		T10	5
valid_sources[0x74]	9279	1			T3	6		T9	5		T10	7
valid_sources[0x75]	11286	1			T3	5		T9	6		T10	4
valid_sources[0x76]	8404	1			T3	5		T9	3		T10	2
valid_sources[0x77]	8539	1			T3	2		T9	7		T10	9
valid_sources[0x78]	10950	1			T3	2		T9	6		T10	9
valid_sources[0x79]	11769	1			T3	6		T9	9		T10	2
valid_sources[0x7a]	11680	1			T9	2		T10	4		T11	14
valid_sources[0x7b]	8354	1			T3	4		T9	6		T10	6
valid_sources[0x7c]	11650	1			T3	1		T9	11		T10	5
valid_sources[0x7d]	8363	1			T3	7		T9	8		T10	3
valid_sources[0x7e]	10076	1			T3	3		T9	9		T10	2
valid_sources[0x7f]	9726	1			T3	5		T9	5		T10	5
valid_sources[0x80]	8564	1			T3	10		T9	2		T10	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1203960

1

T1

6875

T3

247

T9

241

values[0x0]

all_enables

biggest_size

141307

1

T1

664

T3

220

T9

316

values[0x1]

all_enables

biggest_size

139885

1

T1

668

T3

239

T9

331