Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	98108125	14337	0	0
claim_transition_if_regwen_rd_A	98108125	1983	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98108125	14337	0	0
T1	153151	1	0	0
T2	65116	0	0	0
T3	24697	0	0	0
T4	166728	8	0	0
T9	35673	0	0	0
T10	28517	0	0	0
T11	3938	0	0	0
T12	35398	0	0	0
T13	1479	0	0	0
T14	137237	3	0	0
T43	0	8	0	0
T91	0	3	0	0
T124	0	2	0	0
T164	0	2	0	0
T165	0	5	0	0
T166	0	1	0	0
T167	0	1	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98108125	1983	0	0
T6	17843	0	0	0
T30	27553	0	0	0
T31	61201	0	0	0
T57	35665	0	0	0
T75	2809	0	0	0
T124	287716	1	0	0
T126	0	93	0	0
T128	0	2	0	0
T137	0	1	0	0
T164	0	2	0	0
T166	0	18	0	0
T167	0	11	0	0
T168	0	63	0	0
T169	0	2	0	0
T170	0	33	0	0
T171	7322	0	0	0
T172	4644	0	0	0
T173	36325	0	0	0
T174	2527	0	0	0