Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1423036	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1634804

1

T1

30

T2

1268

T3

790

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2729566	1			T1	50		T2	1519		T3	540
values[0x0]	163652	1			T1	3		T2	305		T3	291
values[0x1]	164622	1			T1	6		T2	311		T3	293

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1128847	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1928993

1

T1

35

T2

1452

T3

866

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9838	1			T2	13		T3	6		T4	36
valid_sources[0x01]	10426	1			T2	9		T3	5		T4	41
valid_sources[0x02]	10015	1			T2	1		T3	4		T4	46
valid_sources[0x03]	9886	1			T2	6		T3	2		T4	45
valid_sources[0x04]	10569	1			T2	7		T3	5		T4	36
valid_sources[0x05]	9970	1			T2	9		T3	5		T4	42
valid_sources[0x06]	9773	1			T2	1		T3	2		T4	43
valid_sources[0x07]	9853	1			T2	12		T3	4		T4	44
valid_sources[0x08]	12022	1			T2	11		T3	5		T4	47
valid_sources[0x09]	9692	1			T2	4		T3	6		T4	37
valid_sources[0x0a]	9812	1			T2	4		T3	5		T4	36
valid_sources[0x0b]	26132	1			T2	9		T3	6		T4	39
valid_sources[0x0c]	14700	1			T2	4		T3	4		T4	38
valid_sources[0x0d]	10843	1			T2	5		T3	9		T4	55
valid_sources[0x0e]	10925	1			T2	7		T3	8		T4	40
valid_sources[0x0f]	9749	1			T2	1		T3	3		T4	42
valid_sources[0x10]	12999	1			T2	19		T3	1		T4	41
valid_sources[0x11]	10321	1			T2	14		T3	5		T4	34
valid_sources[0x12]	10597	1			T2	7		T3	2		T4	48
valid_sources[0x13]	9553	1			T2	8		T3	4		T4	43
valid_sources[0x14]	10154	1			T3	2		T4	39		T12	3
valid_sources[0x15]	9723	1			T2	1		T3	2		T4	42
valid_sources[0x16]	9918	1			T1	3		T2	6		T3	5
valid_sources[0x17]	11653	1			T2	9		T3	3		T4	50
valid_sources[0x18]	11576	1			T2	3		T3	2		T4	36
valid_sources[0x19]	11425	1			T2	5		T3	10		T4	38
valid_sources[0x1a]	11446	1			T2	5		T3	3		T4	37
valid_sources[0x1b]	9867	1			T2	17		T3	6		T4	48
valid_sources[0x1c]	11657	1			T2	7		T3	1		T4	28
valid_sources[0x1d]	10358	1			T2	11		T3	7		T4	51
valid_sources[0x1e]	9984	1			T2	6		T3	4		T4	56
valid_sources[0x1f]	9724	1			T2	14		T3	1		T4	43
valid_sources[0x20]	9687	1			T2	10		T3	2		T4	33
valid_sources[0x21]	10155	1			T4	29		T12	1		T14	2
valid_sources[0x22]	14933	1			T2	1		T3	3		T4	49
valid_sources[0x23]	9851	1			T2	7		T3	5		T4	38
valid_sources[0x24]	9897	1			T2	8		T4	42		T12	1
valid_sources[0x25]	11994	1			T2	4		T3	2		T4	30
valid_sources[0x26]	15051	1			T2	18		T3	3		T4	41
valid_sources[0x27]	11520	1			T2	6		T3	2		T4	48
valid_sources[0x28]	9717	1			T2	5		T4	56		T12	1
valid_sources[0x29]	10024	1			T2	5		T3	1		T4	46
valid_sources[0x2a]	10272	1			T1	6		T2	5		T3	5
valid_sources[0x2b]	9734	1			T2	26		T3	7		T4	45
valid_sources[0x2c]	10505	1			T2	7		T3	10		T4	47
valid_sources[0x2d]	11476	1			T2	15		T3	8		T4	48
valid_sources[0x2e]	10016	1			T2	20		T3	8		T4	46
valid_sources[0x2f]	10225	1			T3	4		T4	38		T14	3
valid_sources[0x30]	11238	1			T2	16		T3	10		T4	36
valid_sources[0x31]	10116	1			T1	1		T2	6		T3	9
valid_sources[0x32]	9554	1			T2	6		T3	8		T4	35
valid_sources[0x33]	10013	1			T2	17		T3	3		T4	44
valid_sources[0x34]	10026	1			T2	4		T3	11		T4	46
valid_sources[0x35]	9520	1			T2	26		T3	6		T4	46
valid_sources[0x36]	10483	1			T2	10		T3	6		T4	28
valid_sources[0x37]	9629	1			T2	20		T3	7		T4	38
valid_sources[0x38]	103586	1			T2	19		T3	8		T4	33
valid_sources[0x39]	9928	1			T2	12		T4	41		T14	1
valid_sources[0x3a]	9520	1			T2	6		T3	2		T4	42
valid_sources[0x3b]	9820	1			T2	10		T3	1		T4	45
valid_sources[0x3c]	10142	1			T2	3		T3	11		T4	44
valid_sources[0x3d]	9934	1			T3	7		T4	38		T12	1
valid_sources[0x3e]	10014	1			T2	8		T3	3		T4	36
valid_sources[0x3f]	9602	1			T2	16		T3	3		T4	35
valid_sources[0x40]	42629	1			T2	13		T3	8		T4	52
valid_sources[0x41]	14441	1			T2	5		T3	8		T4	36
valid_sources[0x42]	15294	1			T2	4		T3	7		T4	48
valid_sources[0x43]	12658	1			T3	5		T4	42		T15	3
valid_sources[0x44]	10892	1			T2	4		T3	7		T4	45
valid_sources[0x45]	10115	1			T1	1		T2	7		T3	4
valid_sources[0x46]	9779	1			T3	6		T4	51		T14	2
valid_sources[0x47]	21035	1			T2	17		T3	10		T4	37
valid_sources[0x48]	10292	1			T2	17		T3	4		T4	36
valid_sources[0x49]	12048	1			T2	2		T3	7		T4	39
valid_sources[0x4a]	14150	1			T2	7		T3	6		T4	38
valid_sources[0x4b]	9836	1			T2	16		T3	8		T4	48
valid_sources[0x4c]	11685	1			T2	8		T3	1		T4	48
valid_sources[0x4d]	10545	1			T2	10		T3	3		T4	33
valid_sources[0x4e]	10436	1			T1	1		T2	2		T3	3
valid_sources[0x4f]	12166	1			T2	10		T3	1		T4	47
valid_sources[0x50]	18077	1			T2	6		T4	39		T14	3
valid_sources[0x51]	10093	1			T2	10		T3	1		T4	36
valid_sources[0x52]	9910	1			T2	10		T3	12		T4	46
valid_sources[0x53]	10140	1			T2	1		T3	6		T4	41
valid_sources[0x54]	11217	1			T1	7		T2	17		T3	4
valid_sources[0x55]	10212	1			T2	1		T3	3		T4	43
valid_sources[0x56]	10067	1			T3	7		T4	42		T12	3
valid_sources[0x57]	11153	1			T2	7		T3	1		T4	41
valid_sources[0x58]	10608	1			T2	6		T3	1		T4	40
valid_sources[0x59]	15099	1			T2	8		T3	4		T4	37
valid_sources[0x5a]	9877	1			T2	14		T3	3		T4	30
valid_sources[0x5b]	9954	1			T2	7		T3	3		T4	56
valid_sources[0x5c]	9769	1			T2	10		T3	2		T4	47
valid_sources[0x5d]	9939	1			T1	2		T2	2		T3	5
valid_sources[0x5e]	10096	1			T2	7		T3	2		T4	44
valid_sources[0x5f]	9896	1			T1	2		T2	19		T3	1
valid_sources[0x60]	10000	1			T2	17		T3	1		T4	33
valid_sources[0x61]	10331	1			T3	5		T4	37		T12	1
valid_sources[0x62]	9684	1			T2	1		T3	8		T4	48
valid_sources[0x63]	10172	1			T2	11		T3	6		T4	40
valid_sources[0x64]	10143	1			T2	3		T3	8		T4	35
valid_sources[0x65]	13152	1			T2	9		T3	1		T4	32
valid_sources[0x66]	12345	1			T2	4		T3	4		T4	52
valid_sources[0x67]	11973	1			T2	7		T3	3		T4	36
valid_sources[0x68]	11514	1			T2	3		T3	4		T4	50
valid_sources[0x69]	13712	1			T2	7		T3	11		T4	41
valid_sources[0x6a]	9812	1			T2	4		T3	6		T4	32
valid_sources[0x6b]	51410	1			T2	4		T3	4		T4	38
valid_sources[0x6c]	39425	1			T2	2		T4	41		T12	2
valid_sources[0x6d]	21143	1			T2	11		T3	7		T4	42
valid_sources[0x6e]	10354	1			T2	1		T3	2		T4	42
valid_sources[0x6f]	9675	1			T2	21		T3	3		T4	53
valid_sources[0x70]	9421	1			T1	2		T2	12		T3	8
valid_sources[0x71]	9986	1			T2	6		T3	9		T4	31
valid_sources[0x72]	9591	1			T2	14		T3	8		T4	32
valid_sources[0x73]	10533	1			T2	5		T3	6		T4	34
valid_sources[0x74]	10303	1			T1	2		T2	15		T3	1
valid_sources[0x75]	11384	1			T2	3		T4	37		T25	3
valid_sources[0x76]	9788	1			T2	3		T3	7		T4	41
valid_sources[0x77]	10890	1			T2	11		T3	3		T4	42
valid_sources[0x78]	9559	1			T2	10		T3	3		T4	39
valid_sources[0x79]	9571	1			T2	13		T3	2		T4	45
valid_sources[0x7a]	9873	1			T2	2		T3	1		T4	37
valid_sources[0x7b]	9719	1			T2	17		T3	8		T4	49
valid_sources[0x7c]	11317	1			T2	4		T3	4		T4	46
valid_sources[0x7d]	10293	1			T2	4		T3	10		T4	44
valid_sources[0x7e]	9705	1			T2	14		T4	40		T12	1
valid_sources[0x7f]	9936	1			T2	6		T3	3		T4	35
valid_sources[0x80]	17391	1			T2	26		T3	10		T4	43

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1351536

1

T1

23

T2

736

T3

284

values[0x0]

all_enables

biggest_size

141923

1

T1

2

T2

261

T3

252

values[0x1]

all_enables

biggest_size

141345

1

T1

5

T2

271

T3

254