Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	95490826	12723	0	0
claim_transition_if_regwen_rd_A	95490826	821	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95490826	12723	0	0
T51	0	3	0	0
T55	449123	1	0	0
T67	0	4	0	0
T127	0	1	0	0
T170	0	13	0	0
T171	0	9	0	0
T172	0	3	0	0
T173	0	6	0	0
T174	0	8	0	0
T175	0	4	0	0
T176	21820	0	0	0
T177	6450	0	0	0
T178	24995	0	0	0
T179	1786	0	0	0
T180	113857	0	0	0
T181	28884	0	0	0
T182	38502	0	0	0
T183	922	0	0	0
T184	7114	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95490826	821	0	0
T89	2629	0	0	0
T127	579701	10	0	0
T135	0	10	0	0
T142	0	5	0	0
T150	0	13	0	0
T162	0	49	0	0
T185	0	12	0	0
T186	0	7	0	0
T187	0	24	0	0
T188	0	9	0	0
T189	0	24	0	0
T190	21641	0	0	0
T191	1289	0	0	0
T192	2365	0	0	0
T193	35068	0	0	0
T194	466575	0	0	0
T195	6970	0	0	0
T196	875	0	0	0
T197	4308	0	0	0