Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1680576	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1891318

1

T1

89

T2

762

T3

907

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3243372	1			T1	102		T2	585		T3	927
values[0x0]	163731	1			T1	27		T2	265		T3	274
values[0x1]	164791	1			T1	27		T2	279		T3	246

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1335511	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2236383

1

T1

104

T2

834

T3

1023

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9145	1			T3	4		T10	3		T4	9
valid_sources[0x01]	107528	1			T3	6		T10	9		T4	2
valid_sources[0x02]	11215	1			T3	8		T10	9		T4	6
valid_sources[0x03]	9547	1			T3	2		T10	8		T4	6
valid_sources[0x04]	12007	1			T3	3		T10	5		T4	5
valid_sources[0x05]	11263	1			T3	4		T10	13		T4	5
valid_sources[0x06]	11430	1			T3	5		T10	12		T4	7
valid_sources[0x07]	9666	1			T3	1		T10	3		T4	3
valid_sources[0x08]	9239	1			T3	1		T10	9		T4	9
valid_sources[0x09]	9654	1			T3	4		T10	7		T4	9
valid_sources[0x0a]	14431	1			T3	5		T10	6		T4	7
valid_sources[0x0b]	9857	1			T3	9		T10	4		T4	12
valid_sources[0x0c]	9211	1			T3	8		T10	14		T4	4
valid_sources[0x0d]	9758	1			T3	9		T10	8		T4	7
valid_sources[0x0e]	9628	1			T3	7		T10	11		T4	9
valid_sources[0x0f]	9309	1			T3	4		T10	1		T4	7
valid_sources[0x10]	9678	1			T3	4		T10	16		T4	9
valid_sources[0x11]	10092	1			T3	2		T10	4		T4	7
valid_sources[0x12]	27235	1			T3	10		T10	12		T4	8
valid_sources[0x13]	9378	1			T3	5		T10	4		T4	11
valid_sources[0x14]	9766	1			T3	7		T10	13		T4	8
valid_sources[0x15]	13975	1			T3	4		T10	5		T4	4
valid_sources[0x16]	9807	1			T3	3		T10	4		T4	4
valid_sources[0x17]	9368	1			T3	8		T10	6		T4	7
valid_sources[0x18]	9218	1			T3	4		T10	8		T4	4
valid_sources[0x19]	10532	1			T3	1		T10	9		T4	14
valid_sources[0x1a]	12745	1			T1	156		T3	5		T10	8
valid_sources[0x1b]	10213	1			T3	6		T10	14		T4	6
valid_sources[0x1c]	9492	1			T3	5		T10	3		T4	4
valid_sources[0x1d]	10054	1			T3	5		T10	6		T4	10
valid_sources[0x1e]	9458	1			T3	7		T10	11		T4	7
valid_sources[0x1f]	9272	1			T3	3		T10	6		T4	8
valid_sources[0x20]	9739	1			T3	4		T10	14		T4	4
valid_sources[0x21]	10216	1			T3	10		T10	6		T4	9
valid_sources[0x22]	41623	1			T3	7		T10	6		T4	7
valid_sources[0x23]	10453	1			T3	3		T10	12		T4	15
valid_sources[0x24]	10956	1			T3	11		T10	12		T4	5
valid_sources[0x25]	10625	1			T3	4		T10	9		T4	7
valid_sources[0x26]	10034	1			T3	6		T10	7		T4	6
valid_sources[0x27]	9794	1			T3	8		T10	24		T4	9
valid_sources[0x28]	21046	1			T3	3		T10	3		T4	13
valid_sources[0x29]	9282	1			T3	11		T10	3		T4	10
valid_sources[0x2a]	27487	1			T3	7		T10	11		T4	11
valid_sources[0x2b]	9886	1			T3	8		T10	14		T4	5
valid_sources[0x2c]	9555	1			T3	5		T10	7		T4	9
valid_sources[0x2d]	9613	1			T3	3		T10	16		T4	5
valid_sources[0x2e]	9406	1			T3	6		T10	11		T4	8
valid_sources[0x2f]	12291	1			T3	5		T10	9		T4	9
valid_sources[0x30]	9774	1			T3	3		T10	4		T4	7
valid_sources[0x31]	10067	1			T3	2		T10	1		T4	10
valid_sources[0x32]	9808	1			T3	4		T10	17		T4	4
valid_sources[0x33]	9826	1			T3	7		T10	8		T4	10
valid_sources[0x34]	9603	1			T3	6		T10	7		T4	3
valid_sources[0x35]	9514	1			T3	7		T10	6		T4	2
valid_sources[0x36]	9499	1			T3	3		T10	6		T4	15
valid_sources[0x37]	9434	1			T3	7		T10	15		T4	5
valid_sources[0x38]	9791	1			T3	1		T10	15		T4	2
valid_sources[0x39]	9225	1			T3	6		T10	5		T4	8
valid_sources[0x3a]	15643	1			T2	1129		T3	6		T10	11
valid_sources[0x3b]	9186	1			T3	3		T10	14		T4	4
valid_sources[0x3c]	14292	1			T3	1		T10	13		T4	4
valid_sources[0x3d]	10702	1			T3	8		T10	4		T4	6
valid_sources[0x3e]	9353	1			T3	5		T10	5		T4	7
valid_sources[0x3f]	9243	1			T3	7		T10	7		T4	4
valid_sources[0x40]	9420	1			T3	6		T10	6		T4	6
valid_sources[0x41]	9294	1			T3	9		T10	4		T4	9
valid_sources[0x42]	9668	1			T3	5		T10	22		T4	11
valid_sources[0x43]	9722	1			T3	8		T10	11		T4	4
valid_sources[0x44]	9458	1			T3	8		T10	7		T4	12
valid_sources[0x45]	9395	1			T3	5		T10	4		T4	7
valid_sources[0x46]	9526	1			T10	14		T4	7		T12	5
valid_sources[0x47]	9311	1			T3	9		T10	19		T4	4
valid_sources[0x48]	9561	1			T3	8		T10	10		T4	5
valid_sources[0x49]	18183	1			T3	3		T10	3		T4	6
valid_sources[0x4a]	9740	1			T3	10		T10	7		T4	8
valid_sources[0x4b]	10486	1			T3	8		T10	10		T4	6
valid_sources[0x4c]	9828	1			T3	5		T10	4		T4	6
valid_sources[0x4d]	9489	1			T3	6		T10	17		T4	9
valid_sources[0x4e]	40853	1			T3	7		T10	12		T4	9
valid_sources[0x4f]	9652	1			T3	9		T10	9		T4	8
valid_sources[0x50]	9368	1			T3	3		T10	7		T4	6
valid_sources[0x51]	40903	1			T3	4		T10	5		T4	6
valid_sources[0x52]	9929	1			T3	5		T10	5		T4	9
valid_sources[0x53]	9499	1			T3	8		T10	7		T4	4
valid_sources[0x54]	9611	1			T3	5		T10	8		T4	9
valid_sources[0x55]	9744	1			T3	8		T10	12		T4	4
valid_sources[0x56]	9445	1			T3	5		T10	11		T4	4
valid_sources[0x57]	9546	1			T3	4		T10	5		T4	11
valid_sources[0x58]	8972	1			T3	6		T10	16		T4	7
valid_sources[0x59]	132559	1			T3	9		T10	5		T4	7
valid_sources[0x5a]	10667	1			T3	5		T10	19		T4	3
valid_sources[0x5b]	9563	1			T3	4		T10	8		T4	7
valid_sources[0x5c]	9590	1			T3	8		T10	7		T4	3
valid_sources[0x5d]	9122	1			T3	11		T10	6		T4	6
valid_sources[0x5e]	9594	1			T3	2		T10	9		T4	4
valid_sources[0x5f]	9327	1			T3	6		T10	8		T4	8
valid_sources[0x60]	10255	1			T3	5		T10	5		T4	10
valid_sources[0x61]	9561	1			T3	7		T10	4		T4	12
valid_sources[0x62]	11066	1			T3	9		T10	7		T4	5
valid_sources[0x63]	9275	1			T3	7		T10	11		T4	11
valid_sources[0x64]	11633	1			T3	1		T10	14		T4	10
valid_sources[0x65]	9653	1			T3	10		T10	12		T4	3
valid_sources[0x66]	9506	1			T3	10		T10	2		T4	5
valid_sources[0x67]	9419	1			T3	1		T10	17		T4	7
valid_sources[0x68]	11640	1			T3	5		T10	6		T4	8
valid_sources[0x69]	9206	1			T3	10		T10	9		T4	11
valid_sources[0x6a]	10947	1			T3	8		T10	7		T4	5
valid_sources[0x6b]	217195	1			T3	6		T10	13		T4	8
valid_sources[0x6c]	9497	1			T3	7		T10	12		T4	1
valid_sources[0x6d]	9346	1			T3	9		T10	3		T4	8
valid_sources[0x6e]	9756	1			T3	5		T10	5		T4	11
valid_sources[0x6f]	9654	1			T3	7		T10	5		T4	6
valid_sources[0x70]	9275	1			T3	3		T10	5		T4	7
valid_sources[0x71]	11679	1			T3	5		T10	8		T4	8
valid_sources[0x72]	9733	1			T3	5		T10	7		T4	6
valid_sources[0x73]	8999	1			T3	5		T10	13		T4	8
valid_sources[0x74]	9469	1			T3	10		T10	3		T4	8
valid_sources[0x75]	9289	1			T3	4		T10	12		T4	6
valid_sources[0x76]	9458	1			T3	12		T10	14		T4	7
valid_sources[0x77]	9759	1			T3	7		T10	10		T4	12
valid_sources[0x78]	9761	1			T3	8		T10	14		T4	5
valid_sources[0x79]	10385	1			T3	8		T10	8		T4	9
valid_sources[0x7a]	10404	1			T3	4		T10	14		T4	2
valid_sources[0x7b]	11174	1			T3	6		T10	22		T4	6
valid_sources[0x7c]	9653	1			T3	9		T10	13		T4	10
valid_sources[0x7d]	10222	1			T3	5		T10	4		T4	5
valid_sources[0x7e]	9437	1			T3	6		T10	3		T4	14
valid_sources[0x7f]	11471	1			T3	4		T10	6		T4	10
valid_sources[0x80]	9199	1			T3	3		T10	7		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1607664

1

T1

43

T2

285

T3

446

values[0x0]

all_enables

biggest_size

142193

1

T1

24

T2

234

T3

246

values[0x1]

all_enables

biggest_size

141461

1

T1

22

T2

243

T3

215