Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	105242467	15253	0	0
claim_transition_if_regwen_rd_A	105242467	921	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105242467	15253	0	0
T28	30312	0	0	0
T44	392518	0	0	0
T57	0	6	0	0
T62	0	6	0	0
T66	65850	0	0	0
T80	329038	3	0	0
T82	0	1	0	0
T96	268420	0	0	0
T97	0	13	0	0
T106	0	1	0	0
T112	0	1	0	0
T148	0	2	0	0
T149	0	9	0	0
T150	0	3	0	0
T151	27736	0	0	0
T152	29634	0	0	0
T153	16691	0	0	0
T154	808	0	0	0
T155	5196	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105242467	921	0	0
T28	30312	0	0	0
T44	392518	0	0	0
T66	65850	0	0	0
T80	329038	5	0	0
T96	268420	0	0	0
T120	0	51	0	0
T133	0	34	0	0
T148	0	13	0	0
T151	27736	0	0	0
T152	29634	0	0	0
T153	16691	0	0	0
T154	808	0	0	0
T155	5196	0	0	0
T156	0	30	0	0
T157	0	9	0	0
T158	0	38	0	0
T159	0	56	0	0
T160	0	13	0	0
T161	0	1	0	0