Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1559675	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1780437

1

T1

467

T2

202

T10

1270

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2998193	1			T1	271		T2	228		T10	1079
values[0x0]	170600	1			T1	203		T2	48		T10	363
values[0x1]	171319	1			T1	197		T2	56		T10	437

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1238358	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2101754

1

T1

522

T2

229

T10

1408

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11142	1			T10	6		T13	3		T15	8
valid_sources[0x01]	9555	1			T10	7		T13	3		T15	1
valid_sources[0x02]	9859	1			T10	7		T13	7		T15	18
valid_sources[0x03]	10296	1			T10	11		T13	2		T15	11
valid_sources[0x04]	9880	1			T10	17		T13	4		T15	5
valid_sources[0x05]	9975	1			T10	18		T13	4		T15	4
valid_sources[0x06]	29276	1			T10	2		T13	2		T15	1
valid_sources[0x07]	10614	1			T10	5		T13	2		T15	8
valid_sources[0x08]	11344	1			T10	16		T13	4		T15	9
valid_sources[0x09]	9827	1			T13	10		T15	9		T25	13
valid_sources[0x0a]	10276	1			T10	15		T13	3		T15	3
valid_sources[0x0b]	9960	1			T10	14		T13	1		T15	10
valid_sources[0x0c]	10102	1			T10	10		T13	3		T15	3
valid_sources[0x0d]	17414	1			T10	3		T13	5		T15	4
valid_sources[0x0e]	9690	1			T10	1		T15	14		T25	7
valid_sources[0x0f]	11642	1			T10	3		T13	3		T15	18
valid_sources[0x10]	9583	1			T13	4		T15	5		T25	8
valid_sources[0x11]	9587	1			T13	5		T15	7		T25	7
valid_sources[0x12]	9676	1			T10	19		T13	4		T15	2
valid_sources[0x13]	9814	1			T13	2		T15	11		T25	10
valid_sources[0x14]	19470	1			T10	1		T13	1		T15	11
valid_sources[0x15]	9901	1			T10	10		T13	1		T15	8
valid_sources[0x16]	11584	1			T10	1		T13	6		T15	13
valid_sources[0x17]	9896	1			T10	4		T13	4		T15	16
valid_sources[0x18]	9659	1			T10	9		T13	3		T15	2
valid_sources[0x19]	9735	1			T10	1		T13	1		T15	6
valid_sources[0x1a]	11120	1			T10	22		T13	4		T15	1
valid_sources[0x1b]	11132	1			T10	13		T13	1		T15	6
valid_sources[0x1c]	9595	1			T10	8		T13	3		T15	11
valid_sources[0x1d]	11080	1			T1	671		T10	26		T13	5
valid_sources[0x1e]	10952	1			T10	3		T13	7		T15	4
valid_sources[0x1f]	9820	1			T13	7		T15	2		T25	11
valid_sources[0x20]	10118	1			T13	8		T15	10		T25	3
valid_sources[0x21]	10538	1			T10	1		T13	6		T15	5
valid_sources[0x22]	35650	1			T10	3		T13	4		T15	13
valid_sources[0x23]	9912	1			T10	2		T13	10		T15	10
valid_sources[0x24]	9727	1			T10	6		T13	12		T15	1
valid_sources[0x25]	9769	1			T10	1		T15	5		T25	5
valid_sources[0x26]	10102	1			T10	8		T13	1		T15	7
valid_sources[0x27]	9805	1			T13	2		T15	22		T25	9
valid_sources[0x28]	10117	1			T10	1		T13	1		T15	9
valid_sources[0x29]	10156	1			T10	8		T13	5		T15	4
valid_sources[0x2a]	9828	1			T10	5		T13	2		T15	13
valid_sources[0x2b]	10329	1			T10	37		T13	7		T15	8
valid_sources[0x2c]	11209	1			T10	10		T13	2		T25	14
valid_sources[0x2d]	9735	1			T10	24		T13	5		T15	6
valid_sources[0x2e]	9816	1			T10	4		T13	9		T15	8
valid_sources[0x2f]	10491	1			T10	1		T13	8		T15	3
valid_sources[0x30]	9726	1			T10	19		T13	6		T15	11
valid_sources[0x31]	10056	1			T10	3		T13	4		T15	8
valid_sources[0x32]	9875	1			T13	4		T15	1		T25	8
valid_sources[0x33]	9830	1			T10	13		T13	1		T15	13
valid_sources[0x34]	9708	1			T10	2		T13	2		T15	8
valid_sources[0x35]	10654	1			T13	6		T15	5		T25	6
valid_sources[0x36]	9882	1			T10	24		T13	7		T15	1
valid_sources[0x37]	109887	1			T10	3		T13	4		T15	12
valid_sources[0x38]	9860	1			T10	6		T13	2		T15	10
valid_sources[0x39]	12676	1			T10	5		T13	3		T14	1
valid_sources[0x3a]	14854	1			T10	15		T13	8		T15	4
valid_sources[0x3b]	10064	1			T10	8		T13	4		T15	7
valid_sources[0x3c]	9703	1			T10	2		T13	3		T15	17
valid_sources[0x3d]	10058	1			T10	6		T13	7		T15	16
valid_sources[0x3e]	10827	1			T10	3		T13	3		T15	5
valid_sources[0x3f]	9501	1			T10	9		T13	3		T15	7
valid_sources[0x40]	20089	1			T10	7		T13	4		T14	1
valid_sources[0x41]	9696	1			T10	9		T13	9		T15	16
valid_sources[0x42]	9840	1			T10	10		T13	1		T15	5
valid_sources[0x43]	11446	1			T10	10		T13	1		T15	13
valid_sources[0x44]	9684	1			T13	7		T15	13		T25	6
valid_sources[0x45]	9785	1			T13	4		T15	23		T25	12
valid_sources[0x46]	9873	1			T10	7		T13	3		T15	4
valid_sources[0x47]	11557	1			T10	3		T13	4		T15	11
valid_sources[0x48]	10453	1			T10	32		T15	7		T25	9
valid_sources[0x49]	9814	1			T13	6		T15	16		T25	10
valid_sources[0x4a]	10703	1			T10	7		T13	3		T25	8
valid_sources[0x4b]	9624	1			T10	15		T13	6		T15	7
valid_sources[0x4c]	10079	1			T10	1		T13	7		T15	15
valid_sources[0x4d]	9344	1			T10	27		T13	3		T15	3
valid_sources[0x4e]	9922	1			T10	21		T25	6		T22	5
valid_sources[0x4f]	10880	1			T10	15		T13	1		T15	2
valid_sources[0x50]	9873	1			T10	10		T13	4		T25	12
valid_sources[0x51]	9856	1			T10	8		T13	2		T15	6
valid_sources[0x52]	9698	1			T13	9		T15	4		T25	4
valid_sources[0x53]	10414	1			T10	4		T13	1		T15	6
valid_sources[0x54]	11633	1			T2	332		T10	1		T13	2
valid_sources[0x55]	9942	1			T10	8		T15	8		T25	8
valid_sources[0x56]	10833	1			T10	13		T13	6		T15	4
valid_sources[0x57]	11437	1			T10	3		T13	2		T15	5
valid_sources[0x58]	9977	1			T10	17		T13	4		T15	11
valid_sources[0x59]	9882	1			T10	3		T13	3		T15	9
valid_sources[0x5a]	10129	1			T13	3		T15	5		T25	7
valid_sources[0x5b]	9831	1			T10	12		T13	6		T15	1
valid_sources[0x5c]	9334	1			T10	14		T13	4		T15	6
valid_sources[0x5d]	10323	1			T13	10		T15	11		T25	7
valid_sources[0x5e]	12369	1			T13	7		T15	3		T25	10
valid_sources[0x5f]	22604	1			T13	3		T15	3		T25	6
valid_sources[0x60]	10481	1			T10	6		T13	4		T15	7
valid_sources[0x61]	9981	1			T10	20		T13	8		T15	12
valid_sources[0x62]	9910	1			T10	4		T15	8		T25	6
valid_sources[0x63]	9941	1			T10	2		T13	3		T15	2
valid_sources[0x64]	9643	1			T10	1		T13	2		T15	5
valid_sources[0x65]	10260	1			T10	2		T13	13		T15	11
valid_sources[0x66]	10173	1			T15	8		T25	9		T22	1
valid_sources[0x67]	10995	1			T10	14		T13	2		T15	8
valid_sources[0x68]	9880	1			T13	4		T15	20		T25	9
valid_sources[0x69]	9730	1			T13	3		T15	7		T25	5
valid_sources[0x6a]	9828	1			T10	29		T13	6		T15	17
valid_sources[0x6b]	10011	1			T10	33		T13	2		T15	11
valid_sources[0x6c]	9870	1			T13	2		T15	4		T25	16
valid_sources[0x6d]	10272	1			T10	3		T13	3		T15	2
valid_sources[0x6e]	86780	1			T10	18		T13	2		T15	7
valid_sources[0x6f]	23450	1			T10	3		T13	1		T15	10
valid_sources[0x70]	10833	1			T10	14		T13	5		T15	6
valid_sources[0x71]	20510	1			T10	6		T14	1		T15	4
valid_sources[0x72]	9653	1			T10	1		T13	3		T15	17
valid_sources[0x73]	10057	1			T10	1		T13	11		T15	9
valid_sources[0x74]	14999	1			T10	30		T13	8		T15	3
valid_sources[0x75]	9498	1			T10	13		T13	5		T15	1
valid_sources[0x76]	9829	1			T10	2		T13	8		T15	1
valid_sources[0x77]	9375	1			T13	4		T15	4		T25	9
valid_sources[0x78]	10060	1			T10	7		T13	7		T15	15
valid_sources[0x79]	10219	1			T10	1		T13	4		T15	10
valid_sources[0x7a]	9877	1			T10	5		T13	3		T15	2
valid_sources[0x7b]	14512	1			T10	11		T12	860		T13	1
valid_sources[0x7c]	11193	1			T13	1		T15	20		T25	3
valid_sources[0x7d]	15960	1			T10	15		T11	1740		T13	8
valid_sources[0x7e]	9986	1			T10	10		T13	2		T15	2
valid_sources[0x7f]	11670	1			T10	1		T13	2		T25	7
valid_sources[0x80]	14310	1			T10	1		T13	6		T15	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1485074

1

T1

118

T2

116

T10

566

values[0x0]

all_enables

biggest_size

148262

1

T1

175

T2

38

T10

320

values[0x1]

all_enables

biggest_size

147101

1

T1

174

T2

48

T10

384