Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	106715954	15564	0	0
claim_transition_if_regwen_rd_A	106715954	1581	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106715954	15564	0	0
T45	443195	1	0	0
T47	291382	3	0	0
T49	0	10	0	0
T50	0	5	0	0
T52	20921	0	0	0
T63	25581	0	0	0
T64	0	8	0	0
T142	0	6	0	0
T145	0	6	0	0
T146	0	1	0	0
T147	0	8	0	0
T148	0	3	0	0
T149	25307	0	0	0
T150	17642	0	0	0
T151	8055	0	0	0
T152	15385	0	0	0
T153	157437	0	0	0
T154	4874	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106715954	1581	0	0
T45	443195	2	0	0
T52	20921	0	0	0
T106	0	35	0	0
T107	0	11	0	0
T113	0	50	0	0
T114	0	14	0	0
T146	0	4	0	0
T152	15385	0	0	0
T153	157437	0	0	0
T154	4874	0	0	0
T155	0	14	0	0
T156	0	10	0	0
T157	0	7	0	0
T158	0	14	0	0
T159	40020	0	0	0
T160	29203	0	0	0
T161	15193	0	0	0
T162	2391	0	0	0
T163	32297	0	0	0