Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1809336	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2034301

1

T1

266

T2

388

T10

853

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3487676	1			T1	204		T2	453		T10	619
values[0x0]	177348	1			T1	83		T2	105		T10	298
values[0x1]	178613	1			T1	101		T2	79		T10	326

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1437627	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2406010

1

T1

296

T2

440

T10

940

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12378	1			T2	1		T14	4		T4	2
valid_sources[0x01]	11856	1			T2	4		T14	5		T4	7
valid_sources[0x02]	14839	1			T2	3		T14	4		T4	1
valid_sources[0x03]	11828	1			T2	1		T10	11		T14	5
valid_sources[0x04]	11473	1			T2	2		T14	5		T24	1
valid_sources[0x05]	28592	1			T10	41		T14	3		T24	1
valid_sources[0x06]	14912	1			T2	6		T13	40		T14	8
valid_sources[0x07]	12455	1			T2	1		T10	12		T14	12
valid_sources[0x08]	12561	1			T14	6		T16	46		T7	3
valid_sources[0x09]	11908	1			T2	1		T10	32		T14	4
valid_sources[0x0a]	13151	1			T2	3		T10	19		T14	10
valid_sources[0x0b]	13516	1			T2	5		T14	3		T4	3
valid_sources[0x0c]	13605	1			T2	1		T10	15		T14	7
valid_sources[0x0d]	11859	1			T2	5		T14	6		T16	22
valid_sources[0x0e]	11899	1			T2	1		T14	5		T4	2
valid_sources[0x0f]	11637	1			T10	29		T14	7		T16	9
valid_sources[0x10]	18517	1			T2	2		T13	10		T14	5
valid_sources[0x11]	11751	1			T2	1		T14	5		T4	1
valid_sources[0x12]	17523	1			T2	5		T10	37		T14	6
valid_sources[0x13]	11718	1			T2	2		T14	3		T4	1
valid_sources[0x14]	12035	1			T2	6		T10	31		T14	3
valid_sources[0x15]	13588	1			T2	2		T14	5		T4	2
valid_sources[0x16]	12248	1			T2	2		T10	52		T14	7
valid_sources[0x17]	57879	1			T12	3		T14	10		T4	1
valid_sources[0x18]	12439	1			T2	8		T14	5		T4	3
valid_sources[0x19]	11830	1			T2	5		T14	7		T4	1
valid_sources[0x1a]	11516	1			T10	11		T14	7		T16	32
valid_sources[0x1b]	18341	1			T2	2		T14	4		T4	2
valid_sources[0x1c]	12572	1			T2	2		T14	4		T4	1
valid_sources[0x1d]	12622	1			T2	4		T14	8		T34	1
valid_sources[0x1e]	12166	1			T14	2		T4	2		T16	13
valid_sources[0x1f]	11734	1			T2	1		T14	6		T4	1
valid_sources[0x20]	18020	1			T2	9		T14	9		T4	1
valid_sources[0x21]	13730	1			T2	2		T10	1		T14	5
valid_sources[0x22]	11711	1			T2	8		T14	3		T16	20
valid_sources[0x23]	11889	1			T13	14		T14	7		T4	2
valid_sources[0x24]	12326	1			T2	3		T10	9		T14	3
valid_sources[0x25]	13505	1			T2	2		T14	5		T24	1
valid_sources[0x26]	14575	1			T2	3		T14	5		T4	1
valid_sources[0x27]	12017	1			T2	4		T10	8		T14	5
valid_sources[0x28]	12348	1			T2	2		T10	9		T14	6
valid_sources[0x29]	12698	1			T2	2		T14	8		T4	1
valid_sources[0x2a]	13647	1			T14	3		T4	4		T16	10
valid_sources[0x2b]	68857	1			T2	6		T14	3		T4	2
valid_sources[0x2c]	12697	1			T14	2		T16	26		T81	4
valid_sources[0x2d]	12117	1			T2	2		T10	1		T13	99
valid_sources[0x2e]	12700	1			T2	3		T14	12		T4	3
valid_sources[0x2f]	13308	1			T10	9		T14	6		T4	2
valid_sources[0x30]	64098	1			T2	1		T14	6		T4	1
valid_sources[0x31]	18219	1			T2	2		T14	1		T4	1
valid_sources[0x32]	11772	1			T2	9		T14	6		T37	1
valid_sources[0x33]	12453	1			T2	2		T13	63		T14	3
valid_sources[0x34]	13922	1			T2	3		T14	9		T16	61
valid_sources[0x35]	12351	1			T2	5		T14	2		T24	1
valid_sources[0x36]	12292	1			T10	4		T14	5		T4	3
valid_sources[0x37]	14849	1			T2	5		T14	8		T4	3
valid_sources[0x38]	13915	1			T10	67		T14	9		T4	2
valid_sources[0x39]	12435	1			T2	3		T14	4		T4	4
valid_sources[0x3a]	13005	1			T14	4		T24	2		T16	81
valid_sources[0x3b]	13208	1			T2	3		T13	20		T14	5
valid_sources[0x3c]	12882	1			T2	2		T14	4		T4	1
valid_sources[0x3d]	12026	1			T2	2		T14	8		T16	27
valid_sources[0x3e]	11967	1			T2	5		T10	7		T14	2
valid_sources[0x3f]	13413	1			T2	4		T14	4		T24	1
valid_sources[0x40]	27913	1			T2	2		T14	12		T16	19
valid_sources[0x41]	11599	1			T2	3		T14	9		T37	1
valid_sources[0x42]	121613	1			T2	2		T14	6		T4	1
valid_sources[0x43]	12600	1			T14	5		T4	2		T16	43
valid_sources[0x44]	12550	1			T2	4		T14	3		T4	4
valid_sources[0x45]	12608	1			T2	2		T13	269		T14	7
valid_sources[0x46]	22849	1			T2	2		T14	9		T4	1
valid_sources[0x47]	11657	1			T2	3		T14	11		T4	1
valid_sources[0x48]	15273	1			T14	2		T24	4		T16	14
valid_sources[0x49]	12494	1			T2	2		T14	8		T16	27
valid_sources[0x4a]	12704	1			T2	1		T14	4		T4	6
valid_sources[0x4b]	12089	1			T2	3		T14	4		T4	2
valid_sources[0x4c]	12358	1			T2	4		T14	4		T24	3
valid_sources[0x4d]	12068	1			T2	2		T14	6		T4	3
valid_sources[0x4e]	11971	1			T2	2		T10	13		T14	10
valid_sources[0x4f]	13802	1			T2	4		T10	12		T14	5
valid_sources[0x50]	14685	1			T2	5		T14	10		T4	1
valid_sources[0x51]	13468	1			T10	36		T14	10		T24	7
valid_sources[0x52]	13065	1			T14	6		T4	1		T24	1
valid_sources[0x53]	11701	1			T2	2		T14	5		T4	1
valid_sources[0x54]	12372	1			T2	4		T10	18		T14	8
valid_sources[0x55]	13831	1			T2	5		T14	2		T34	2
valid_sources[0x56]	11902	1			T14	9		T34	1		T16	29
valid_sources[0x57]	14138	1			T2	2		T14	5		T16	49
valid_sources[0x58]	15247	1			T2	1		T14	11		T4	3
valid_sources[0x59]	12224	1			T11	51		T13	20		T14	3
valid_sources[0x5a]	12147	1			T2	3		T14	9		T4	2
valid_sources[0x5b]	12507	1			T2	1		T14	6		T4	5
valid_sources[0x5c]	14331	1			T2	2		T10	25		T14	4
valid_sources[0x5d]	12897	1			T2	4		T13	59		T14	7
valid_sources[0x5e]	12262	1			T2	2		T13	52		T14	3
valid_sources[0x5f]	12190	1			T2	1		T14	5		T4	1
valid_sources[0x60]	12310	1			T2	4		T10	4		T13	84
valid_sources[0x61]	12205	1			T2	1		T10	1		T14	6
valid_sources[0x62]	12036	1			T2	10		T14	7		T4	2
valid_sources[0x63]	29068	1			T10	11		T14	5		T4	3
valid_sources[0x64]	11910	1			T2	1		T14	6		T4	2
valid_sources[0x65]	38507	1			T2	1		T10	37		T14	1
valid_sources[0x66]	11796	1			T2	5		T14	4		T36	1
valid_sources[0x67]	15711	1			T2	1		T10	13		T14	5
valid_sources[0x68]	12190	1			T2	6		T14	5		T4	1
valid_sources[0x69]	12611	1			T1	388		T2	2		T14	6
valid_sources[0x6a]	12911	1			T2	2		T13	12		T14	7
valid_sources[0x6b]	15571	1			T2	6		T14	4		T4	7
valid_sources[0x6c]	12326	1			T2	2		T14	2		T34	1
valid_sources[0x6d]	12051	1			T2	1		T14	4		T4	1
valid_sources[0x6e]	48429	1			T2	2		T10	19		T14	11
valid_sources[0x6f]	12238	1			T2	5		T14	3		T4	1
valid_sources[0x70]	12053	1			T2	2		T14	2		T34	1
valid_sources[0x71]	12986	1			T2	1		T14	3		T4	3
valid_sources[0x72]	12594	1			T2	4		T14	6		T4	3
valid_sources[0x73]	12190	1			T2	6		T10	21		T14	8
valid_sources[0x74]	11627	1			T10	14		T14	8		T4	2
valid_sources[0x75]	12011	1			T2	1		T14	8		T16	31
valid_sources[0x76]	11886	1			T2	1		T14	7		T4	1
valid_sources[0x77]	12193	1			T2	4		T10	54		T14	5
valid_sources[0x78]	14282	1			T2	3		T14	8		T4	2
valid_sources[0x79]	14447	1			T2	8		T14	6		T4	1
valid_sources[0x7a]	12130	1			T2	3		T13	121		T14	8
valid_sources[0x7b]	12278	1			T2	1		T10	31		T14	4
valid_sources[0x7c]	11993	1			T2	4		T14	6		T4	1
valid_sources[0x7d]	11951	1			T12	26		T14	3		T4	7
valid_sources[0x7e]	11974	1			T2	2		T14	3		T4	1
valid_sources[0x7f]	11843	1			T14	6		T16	30		T81	2
valid_sources[0x80]	12065	1			T2	2		T10	7		T14	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1727722

1

T1

102

T2

228

T10

311

values[0x0]

all_enables

biggest_size

153837

1

T1

75

T2

92

T10

261

values[0x1]

all_enables

biggest_size

152742

1

T1

89

T2

68

T10

281