Unified Coverage Report :: Module :: prim_cdc_rand_delay

Module : prim_cdc_rand_delay

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_cdc_rand_delay_0/rtl/prim_cdc_rand_delay.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay	100.00			100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay	100.00			100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay	100.00			100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay	100.00			100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay	100.00			100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_cdc_rand_delay

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	10	10	100.00
Total Bits 0->1	5	5	100.00
Total Bits 1->0	5	5	100.00

Ports	5	5	100.00
Port Bits	10	10	100.00
Port Bits 0->1	5	5	100.00
Port Bits 1->0	5	5	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prev_data_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
src_data_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
dst_data_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	8	8	100.00
Total Bits 0->1	4	4	100.00
Total Bits 1->0	4	4	100.00

Ports	4	4	100.00
Port Bits	8	8	100.00
Port Bits 0->1	4	4	100.00
Port Bits 1->0	4	4	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prev_data_i	Yes	Yes	T3,T5,T9	Yes	T3,T4,T5	INPUT
src_data_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
dst_data_o	Excluded	Excluded	T3,T4,T5	Excluded	T3,T4,T5	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	10	10	100.00
Total Bits 0->1	5	5	100.00
Total Bits 1->0	5	5	100.00

Ports	5	5	100.00
Port Bits	10	10	100.00
Port Bits 0->1	5	5	100.00
Port Bits 1->0	5	5	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prev_data_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
src_data_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
dst_data_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	10	10	100.00
Total Bits 0->1	5	5	100.00
Total Bits 1->0	5	5	100.00

Ports	5	5	100.00
Port Bits	10	10	100.00
Port Bits 0->1	5	5	100.00
Port Bits 1->0	5	5	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T5,T9	Yes	T3,T4,T5	INPUT
prev_data_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
src_data_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
dst_data_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	10	10	100.00
Total Bits 0->1	5	5	100.00
Total Bits 1->0	5	5	100.00

Ports	5	5	100.00
Port Bits	10	10	100.00
Port Bits 0->1	5	5	100.00
Port Bits 1->0	5	5	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T5,T9	Yes	T3,T4,T5	INPUT
prev_data_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
src_data_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
dst_data_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	10	10	100.00
Total Bits 0->1	5	5	100.00
Total Bits 1->0	5	5	100.00

Ports	5	5	100.00
Port Bits	10	10	100.00
Port Bits 0->1	5	5	100.00
Port Bits 1->0	5	5	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prev_data_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
src_data_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
dst_data_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT