Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	119102354	14735	0	0
claim_transition_if_regwen_rd_A	119102354	1681	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119102354	14735	0	0
T8	28347	0	0	0
T20	313539	2	0	0
T38	354936	0	0	0
T44	0	1	0	0
T47	27466	0	0	0
T54	0	2	0	0
T56	0	6	0	0
T57	3733	0	0	0
T58	24361	0	0	0
T80	0	1	0	0
T131	0	1	0	0
T132	0	3	0	0
T133	0	3	0	0
T134	0	2	0	0
T135	0	9	0	0
T136	28374	0	0	0
T137	6378	0	0	0
T138	5093	0	0	0
T139	13963	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119102354	1681	0	0
T27	49581	0	0	0
T28	30136	0	0	0
T44	281670	3	0	0
T98	0	53	0	0
T107	0	2	0	0
T108	0	9	0	0
T115	0	95	0	0
T134	0	9	0	0
T140	0	6	0	0
T141	0	9	0	0
T142	0	211	0	0
T143	0	30	0	0
T144	41972	0	0	0
T145	1456	0	0	0
T146	8314	0	0	0
T147	39370	0	0	0
T148	8363	0	0	0
T149	3349	0	0	0
T150	9749	0	0	0