Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1697852	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1916277

1

T1

237

T2

868

T3

1315

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3267864	1			T1	250		T2	482		T3	1526
values[0x0]	172505	1			T1	66		T2	381		T3	321
values[0x1]	173760	1			T1	70		T2	387		T3	343

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1348634	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2265495

1

T1

268

T2

968

T3

1500

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7420	1			T2	1		T3	7		T11	3
valid_sources[0x01]	7489	1			T1	2		T2	4		T3	16
valid_sources[0x02]	8201	1			T2	3		T3	3		T9	3
valid_sources[0x03]	7777	1			T1	3		T2	7		T3	3
valid_sources[0x04]	9174	1			T2	7		T3	14		T9	3
valid_sources[0x05]	7312	1			T1	3		T2	10		T3	17
valid_sources[0x06]	7860	1			T1	3		T2	5		T3	6
valid_sources[0x07]	7803	1			T2	4		T3	15		T9	8
valid_sources[0x08]	9149	1			T1	2		T2	7		T3	1
valid_sources[0x09]	7547	1			T2	11		T3	9		T9	6
valid_sources[0x0a]	7827	1			T1	6		T2	7		T3	9
valid_sources[0x0b]	9704	1			T1	1		T2	6		T3	8
valid_sources[0x0c]	9426	1			T2	7		T3	7		T11	7
valid_sources[0x0d]	7427	1			T1	2		T2	1		T3	5
valid_sources[0x0e]	7658	1			T1	1		T2	6		T3	2
valid_sources[0x0f]	7453	1			T1	4		T2	2		T3	5
valid_sources[0x10]	10583	1			T3	3		T9	6		T10	1
valid_sources[0x11]	11224	1			T1	2		T2	4		T3	10
valid_sources[0x12]	7674	1			T2	9		T3	11		T9	6
valid_sources[0x13]	7482	1			T2	5		T3	12		T9	3
valid_sources[0x14]	7383	1			T1	3		T2	3		T3	4
valid_sources[0x15]	7995	1			T2	1		T3	15		T10	1
valid_sources[0x16]	9540	1			T2	5		T3	11		T9	4
valid_sources[0x17]	7616	1			T2	8		T3	16		T9	1
valid_sources[0x18]	7326	1			T1	1		T2	5		T3	4
valid_sources[0x19]	7367	1			T2	6		T3	10		T9	3
valid_sources[0x1a]	7574	1			T1	2		T2	5		T3	8
valid_sources[0x1b]	9310	1			T1	8		T2	1		T3	10
valid_sources[0x1c]	169543	1			T1	7		T3	6		T9	5
valid_sources[0x1d]	7487	1			T2	11		T3	10		T11	5
valid_sources[0x1e]	7576	1			T3	11		T9	7		T11	1
valid_sources[0x1f]	11431	1			T2	5		T3	9		T9	11
valid_sources[0x20]	10398	1			T1	3		T2	1		T3	11
valid_sources[0x21]	7745	1			T1	1		T2	10		T3	5
valid_sources[0x22]	7599	1			T1	5		T2	10		T3	8
valid_sources[0x23]	7313	1			T2	4		T3	13		T9	9
valid_sources[0x24]	22036	1			T1	6		T2	3		T3	10
valid_sources[0x25]	19362	1			T2	3		T3	12		T9	6
valid_sources[0x26]	7559	1			T1	7		T2	2		T3	12
valid_sources[0x27]	7406	1			T1	1		T2	3		T3	17
valid_sources[0x28]	9174	1			T3	4		T9	2		T11	3
valid_sources[0x29]	8437	1			T2	7		T3	5		T9	13
valid_sources[0x2a]	7750	1			T2	6		T3	6		T9	2
valid_sources[0x2b]	7496	1			T2	15		T3	4		T9	4
valid_sources[0x2c]	8047	1			T1	1		T2	4		T3	3
valid_sources[0x2d]	98076	1			T1	1		T2	5		T3	7
valid_sources[0x2e]	15206	1			T2	12		T3	7		T9	7
valid_sources[0x2f]	37716	1			T2	14		T3	3		T11	1
valid_sources[0x30]	12921	1			T2	2		T3	9		T9	5
valid_sources[0x31]	7632	1			T1	6		T2	2		T3	9
valid_sources[0x32]	39459	1			T2	5		T3	5		T9	4
valid_sources[0x33]	7650	1			T1	5		T2	2		T3	3
valid_sources[0x34]	8352	1			T1	2		T2	7		T3	5
valid_sources[0x35]	7685	1			T2	2		T3	6		T9	5
valid_sources[0x36]	11892	1			T2	3		T3	5		T9	5
valid_sources[0x37]	9037	1			T1	1		T2	5		T3	7
valid_sources[0x38]	7999	1			T1	2		T2	5		T3	6
valid_sources[0x39]	7999	1			T2	6		T3	16		T9	2
valid_sources[0x3a]	9396	1			T1	1		T2	5		T3	7
valid_sources[0x3b]	7611	1			T3	5		T9	1		T12	1
valid_sources[0x3c]	7476	1			T2	16		T3	9		T9	1
valid_sources[0x3d]	7740	1			T2	4		T3	12		T10	2
valid_sources[0x3e]	7562	1			T2	4		T3	6		T9	6
valid_sources[0x3f]	7497	1			T2	3		T3	5		T9	4
valid_sources[0x40]	8475	1			T2	4		T3	12		T12	1
valid_sources[0x41]	6873	1			T1	1		T2	4		T3	15
valid_sources[0x42]	46149	1			T2	3		T3	11		T9	8
valid_sources[0x43]	8986	1			T1	7		T2	10		T3	17
valid_sources[0x44]	7668	1			T2	5		T3	13		T9	3
valid_sources[0x45]	8196	1			T2	9		T3	2		T9	2
valid_sources[0x46]	7459	1			T1	7		T2	19		T3	18
valid_sources[0x47]	8683	1			T3	7		T9	9		T11	5
valid_sources[0x48]	7623	1			T1	4		T2	7		T3	8
valid_sources[0x49]	7856	1			T1	2		T2	9		T3	11
valid_sources[0x4a]	9209	1			T2	4		T3	13		T9	3
valid_sources[0x4b]	9233	1			T2	6		T3	12		T9	1
valid_sources[0x4c]	8504	1			T1	3		T2	17		T3	12
valid_sources[0x4d]	7434	1			T1	1		T2	7		T9	6
valid_sources[0x4e]	8603	1			T1	4		T3	9		T11	5
valid_sources[0x4f]	7565	1			T1	1		T2	2		T3	5
valid_sources[0x50]	8232	1			T1	2		T2	2		T3	8
valid_sources[0x51]	7331	1			T2	8		T3	8		T9	3
valid_sources[0x52]	9437	1			T1	1		T2	4		T3	7
valid_sources[0x53]	8123	1			T1	4		T3	3		T9	1
valid_sources[0x54]	9737	1			T1	2		T2	3		T3	5
valid_sources[0x55]	7871	1			T2	4		T3	11		T9	5
valid_sources[0x56]	37785	1			T1	5		T2	2		T3	9
valid_sources[0x57]	7525	1			T1	1		T2	1		T3	7
valid_sources[0x58]	7618	1			T2	7		T3	18		T11	5
valid_sources[0x59]	7599	1			T3	11		T9	11		T11	2
valid_sources[0x5a]	7632	1			T2	3		T3	12		T9	3
valid_sources[0x5b]	8567	1			T1	2		T2	7		T3	11
valid_sources[0x5c]	7492	1			T2	7		T3	5		T9	7
valid_sources[0x5d]	7538	1			T1	2		T2	3		T3	13
valid_sources[0x5e]	7974	1			T2	5		T3	17		T4	1
valid_sources[0x5f]	12800	1			T2	1		T3	8		T11	3
valid_sources[0x60]	10315	1			T2	6		T3	7		T9	1
valid_sources[0x61]	8039	1			T1	1		T2	5		T3	12
valid_sources[0x62]	35136	1			T1	7		T2	5		T3	5
valid_sources[0x63]	11977	1			T1	2		T2	6		T3	13
valid_sources[0x64]	13914	1			T2	6		T3	6		T9	2
valid_sources[0x65]	9517	1			T2	5		T3	6		T9	1
valid_sources[0x66]	7449	1			T1	12		T2	6		T3	5
valid_sources[0x67]	8298	1			T1	2		T2	3		T3	15
valid_sources[0x68]	7738	1			T1	5		T2	4		T3	8
valid_sources[0x69]	7711	1			T2	1		T3	6		T9	1
valid_sources[0x6a]	50183	1			T2	2		T3	5		T9	3
valid_sources[0x6b]	7798	1			T1	1		T2	1		T3	10
valid_sources[0x6c]	17317	1			T2	5		T3	7		T9	2
valid_sources[0x6d]	7394	1			T3	6		T9	14		T12	1
valid_sources[0x6e]	7029	1			T1	3		T2	4		T3	5
valid_sources[0x6f]	16725	1			T1	1		T2	9		T3	14
valid_sources[0x70]	7787	1			T1	3		T2	1		T3	15
valid_sources[0x71]	7642	1			T2	7		T3	9		T11	1
valid_sources[0x72]	9145	1			T1	3		T2	6		T3	5
valid_sources[0x73]	8327	1			T1	2		T2	1		T3	6
valid_sources[0x74]	7770	1			T2	1		T3	7		T9	1
valid_sources[0x75]	14042	1			T2	13		T3	8		T9	1
valid_sources[0x76]	7818	1			T1	1		T3	17		T9	22
valid_sources[0x77]	7733	1			T2	8		T3	10		T9	4
valid_sources[0x78]	7975	1			T1	1		T2	7		T3	4
valid_sources[0x79]	7468	1			T1	5		T2	5		T3	3
valid_sources[0x7a]	9274	1			T1	2		T2	13		T3	6
valid_sources[0x7b]	7648	1			T1	1		T2	10		T3	9
valid_sources[0x7c]	7710	1			T1	6		T2	4		T3	10
valid_sources[0x7d]	7688	1			T1	3		T2	8		T3	8
valid_sources[0x7e]	7581	1			T3	14		T9	2		T4	1
valid_sources[0x7f]	7577	1			T2	9		T3	29		T9	14
valid_sources[0x80]	72108	1			T1	4		T3	6		T9	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1618016

1

T1

123

T2

213

T3

736

values[0x0]

all_enables

biggest_size

149527

1

T1

55

T2

332

T3

280

values[0x1]

all_enables

biggest_size

148734

1

T1

59

T2

323

T3

299