Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	106806977	13414	0	0
claim_transition_if_regwen_rd_A	106806977	1350	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106806977	13414	0	0
T7	39783	0	0	0
T8	72544	0	0	0
T28	375233	19	0	0
T29	282986	0	0	0
T39	237826	0	0	0
T44	0	22	0	0
T63	0	1	0	0
T74	0	3	0	0
T79	1698	0	0	0
T81	0	7	0	0
T88	0	1	0	0
T89	0	17	0	0
T126	0	4	0	0
T127	0	14	0	0
T128	0	2	0	0
T129	36605	0	0	0
T130	38243	0	0	0
T131	11584	0	0	0
T132	19162	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106806977	1350	0	0
T88	280327	7	0	0
T92	0	5	0	0
T99	0	3	0	0
T120	0	6	0	0
T122	0	10	0	0
T126	0	4	0	0
T133	0	15	0	0
T134	0	3	0	0
T135	0	9	0	0
T136	0	107	0	0
T137	25696	0	0	0
T138	59852	0	0	0
T139	31857	0	0	0
T140	189814	0	0	0
T141	76432	0	0	0
T142	8173	0	0	0
T143	6673	0	0	0
T144	54596	0	0	0
T145	6794	0	0	0