Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	907576	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1099937

1

T1

5

T2

210

T3

39

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1713357	1			T1	13		T2	255		T3	43
values[0x0]	146628	1			T1	3		T2	48		T3	10
values[0x1]	147528	1			T1	5		T2	65		T3	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	718326	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1289187

1

T1

7

T2

253

T3

42

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6069	1			T13	9		T17	2		T19	1
valid_sources[0x01]	5836	1			T2	6		T3	7		T5	17
valid_sources[0x02]	6302	1			T2	10		T13	6		T17	14
valid_sources[0x03]	6147	1			T13	10		T17	10		T27	8
valid_sources[0x04]	7522	1			T13	5		T17	4		T27	5
valid_sources[0x05]	6016	1			T13	6		T17	7		T27	3
valid_sources[0x06]	5952	1			T13	3		T17	4		T14	4
valid_sources[0x07]	6128	1			T13	2		T17	6		T14	12
valid_sources[0x08]	8458	1			T6	4		T13	6		T17	5
valid_sources[0x09]	5926	1			T2	11		T13	6		T17	2
valid_sources[0x0a]	5851	1			T2	26		T13	2		T17	2
valid_sources[0x0b]	6442	1			T13	1		T17	5		T19	2
valid_sources[0x0c]	6673	1			T13	13		T17	8		T14	9
valid_sources[0x0d]	5911	1			T13	4		T17	4		T14	13
valid_sources[0x0e]	8236	1			T13	11		T17	13		T19	1
valid_sources[0x0f]	8250	1			T13	6		T17	8		T14	6
valid_sources[0x10]	5926	1			T2	4		T13	5		T14	1
valid_sources[0x11]	6182	1			T13	4		T17	4		T14	10
valid_sources[0x12]	6037	1			T2	3		T13	1		T17	12
valid_sources[0x13]	6055	1			T2	2		T13	2		T17	4
valid_sources[0x14]	6501	1			T13	6		T17	9		T14	2
valid_sources[0x15]	5809	1			T2	3		T6	21		T13	12
valid_sources[0x16]	6367	1			T13	3		T17	9		T27	3
valid_sources[0x17]	5924	1			T13	4		T17	13		T14	8
valid_sources[0x18]	5954	1			T1	2		T13	5		T17	5
valid_sources[0x19]	6282	1			T13	2		T17	11		T27	5
valid_sources[0x1a]	6318	1			T13	6		T17	6		T14	3
valid_sources[0x1b]	5883	1			T13	13		T17	7		T14	4
valid_sources[0x1c]	7930	1			T5	18		T13	1		T17	11
valid_sources[0x1d]	5895	1			T13	3		T17	3		T14	6
valid_sources[0x1e]	12853	1			T1	2		T13	6		T17	2
valid_sources[0x1f]	5995	1			T5	1		T13	3		T17	8
valid_sources[0x20]	8397	1			T2	9		T13	6		T17	19
valid_sources[0x21]	6119	1			T13	6		T17	12		T14	12
valid_sources[0x22]	6389	1			T2	11		T3	4		T17	8
valid_sources[0x23]	6392	1			T13	9		T17	8		T14	19
valid_sources[0x24]	25687	1			T13	4		T18	17		T17	2
valid_sources[0x25]	6386	1			T3	3		T13	13		T17	2
valid_sources[0x26]	6009	1			T13	10		T17	4		T19	1
valid_sources[0x27]	7024	1			T6	3		T13	4		T17	10
valid_sources[0x28]	5862	1			T13	6		T17	4		T14	1
valid_sources[0x29]	6112	1			T13	7		T17	7		T27	1
valid_sources[0x2a]	6858	1			T13	6		T17	7		T27	3
valid_sources[0x2b]	9741	1			T5	65		T13	1		T17	2
valid_sources[0x2c]	8734	1			T13	7		T17	4		T27	2
valid_sources[0x2d]	6970	1			T13	10		T17	3		T27	4
valid_sources[0x2e]	6654	1			T13	9		T17	3		T19	1
valid_sources[0x2f]	6008	1			T13	8		T17	7		T14	3
valid_sources[0x30]	7007	1			T2	2		T13	3		T17	10
valid_sources[0x31]	6301	1			T3	8		T13	4		T17	6
valid_sources[0x32]	6319	1			T3	2		T13	1		T17	5
valid_sources[0x33]	5614	1			T2	10		T13	3		T17	11
valid_sources[0x34]	5764	1			T3	1		T17	7		T27	2
valid_sources[0x35]	8591	1			T2	2		T13	1		T17	11
valid_sources[0x36]	5695	1			T13	3		T17	6		T14	3
valid_sources[0x37]	6110	1			T13	2		T17	1		T27	2
valid_sources[0x38]	8116	1			T13	14		T17	4		T14	6
valid_sources[0x39]	6024	1			T13	7		T17	6		T27	4
valid_sources[0x3a]	6085	1			T13	3		T17	3		T14	6
valid_sources[0x3b]	6362	1			T13	2		T17	9		T14	2
valid_sources[0x3c]	5970	1			T2	11		T6	8		T13	6
valid_sources[0x3d]	6055	1			T13	7		T17	7		T14	22
valid_sources[0x3e]	6102	1			T13	1		T17	11		T27	1
valid_sources[0x3f]	13421	1			T13	12		T17	5		T27	1
valid_sources[0x40]	6659	1			T13	4		T17	9		T14	2
valid_sources[0x41]	5853	1			T13	9		T17	5		T27	3
valid_sources[0x42]	6331	1			T3	1		T17	4		T95	1
valid_sources[0x43]	6398	1			T13	1		T17	19		T14	6
valid_sources[0x44]	5958	1			T2	1		T13	2		T17	6
valid_sources[0x45]	5715	1			T13	6		T17	8		T19	1
valid_sources[0x46]	6096	1			T13	4		T17	5		T19	1
valid_sources[0x47]	5910	1			T6	2		T13	10		T17	1
valid_sources[0x48]	6410	1			T13	1		T17	3		T14	4
valid_sources[0x49]	5898	1			T13	4		T17	9		T27	5
valid_sources[0x4a]	5803	1			T2	2		T13	7		T17	4
valid_sources[0x4b]	6848	1			T13	9		T17	7		T27	8
valid_sources[0x4c]	5681	1			T13	2		T17	7		T41	1
valid_sources[0x4d]	6585	1			T13	5		T17	8		T27	2
valid_sources[0x4e]	5855	1			T3	4		T13	6		T17	17
valid_sources[0x4f]	6129	1			T13	9		T17	1		T14	3
valid_sources[0x50]	9785	1			T13	5		T17	19		T14	3
valid_sources[0x51]	7171	1			T13	5		T17	2		T27	7
valid_sources[0x52]	5857	1			T13	6		T17	8		T27	2
valid_sources[0x53]	6128	1			T13	5		T17	3		T14	8
valid_sources[0x54]	6089	1			T13	3		T17	8		T14	15
valid_sources[0x55]	7050	1			T13	3		T17	8		T19	1
valid_sources[0x56]	7902	1			T13	14		T17	6		T14	9
valid_sources[0x57]	8521	1			T13	7		T17	5		T19	2
valid_sources[0x58]	6039	1			T2	5		T13	9		T17	2
valid_sources[0x59]	5708	1			T13	14		T17	9		T89	26
valid_sources[0x5a]	5994	1			T13	6		T17	8		T19	1
valid_sources[0x5b]	5872	1			T13	1		T17	13		T14	5
valid_sources[0x5c]	6331	1			T13	5		T14	1		T27	6
valid_sources[0x5d]	6293	1			T13	5		T17	6		T19	1
valid_sources[0x5e]	8152	1			T13	9		T17	11		T14	3
valid_sources[0x5f]	6058	1			T3	1		T13	8		T17	3
valid_sources[0x60]	6527	1			T13	2		T17	4		T27	5
valid_sources[0x61]	6045	1			T13	11		T17	3		T14	16
valid_sources[0x62]	6192	1			T13	1		T17	3		T27	4
valid_sources[0x63]	7013	1			T13	9		T17	9		T27	4
valid_sources[0x64]	6057	1			T13	4		T17	5		T27	2
valid_sources[0x65]	5844	1			T5	4		T13	3		T17	4
valid_sources[0x66]	6300	1			T1	4		T13	9		T17	2
valid_sources[0x67]	6222	1			T5	1		T13	4		T17	1
valid_sources[0x68]	6286	1			T13	3		T17	16		T14	14
valid_sources[0x69]	8994	1			T13	3		T17	5		T14	1
valid_sources[0x6a]	5929	1			T13	5		T17	3		T19	1
valid_sources[0x6b]	5858	1			T13	5		T17	8		T27	4
valid_sources[0x6c]	6650	1			T2	1		T5	3		T13	1
valid_sources[0x6d]	5885	1			T13	4		T17	11		T27	4
valid_sources[0x6e]	6229	1			T13	3		T18	34		T17	3
valid_sources[0x6f]	6113	1			T2	1		T13	2		T17	5
valid_sources[0x70]	6040	1			T13	12		T17	6		T27	2
valid_sources[0x71]	45085	1			T2	1		T6	1		T17	7
valid_sources[0x72]	7102	1			T13	14		T17	4		T27	4
valid_sources[0x73]	6646	1			T13	8		T17	8		T27	1
valid_sources[0x74]	6121	1			T13	2		T17	13		T27	7
valid_sources[0x75]	5765	1			T13	7		T17	8		T14	2
valid_sources[0x76]	11969	1			T13	2		T17	4		T14	4
valid_sources[0x77]	6412	1			T5	14		T13	3		T17	6
valid_sources[0x78]	7397	1			T5	6		T13	5		T17	6
valid_sources[0x79]	5955	1			T13	4		T17	2		T14	5
valid_sources[0x7a]	6041	1			T6	1		T13	5		T17	3
valid_sources[0x7b]	5809	1			T13	1		T18	17		T17	10
valid_sources[0x7c]	5792	1			T13	5		T17	6		T19	1
valid_sources[0x7d]	5980	1			T6	3		T13	3		T17	9
valid_sources[0x7e]	6027	1			T2	11		T13	7		T17	10
valid_sources[0x7f]	5891	1			T13	4		T17	3		T14	2
valid_sources[0x80]	6111	1			T13	1		T17	5		T27	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

846434

1

T2

114

T3

19

T12

1

values[0x0]

all_enables

biggest_size

127194

1

T1

1

T2

42

T3

8

values[0x1]

all_enables

biggest_size

126309

1

T1

4

T2

54

T3

12