Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	60179982	13660	0	0
claim_transition_if_regwen_rd_A	60179982	901	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60179982	13660	0	0
T49	0	2	0	0
T100	310681	5	0	0
T101	0	2	0	0
T102	0	12	0	0
T116	10074	0	0	0
T155	0	5	0	0
T159	0	3	0	0
T160	0	14	0	0
T161	0	3	0	0
T162	0	8	0	0
T163	0	9	0	0
T164	24274	0	0	0
T165	15991	0	0	0
T166	433576	0	0	0
T167	61408	0	0	0
T168	146196	0	0	0
T169	31060	0	0	0
T170	2644	0	0	0
T171	39190	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60179982	901	0	0
T49	280021	6	0	0
T123	0	11	0	0
T124	0	34	0	0
T131	0	30	0	0
T161	0	1	0	0
T172	0	9	0	0
T173	0	14	0	0
T174	0	12	0	0
T175	0	1	0	0
T176	0	6	0	0
T177	440736	0	0	0
T178	1793	0	0	0
T179	300136	0	0	0
T180	1503	0	0	0
T181	225406	0	0	0
T182	1224	0	0	0
T183	22729	0	0	0
T184	15757	0	0	0
T185	27025	0	0	0