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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.96 97.92 96.12 93.40 97.62 98.52 99.00 96.11


Total test records in report: 1000
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T372 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.642459761 Aug 23 10:11:10 PM UTC 24 Aug 23 10:11:17 PM UTC 24 196150383 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.473634729 Aug 23 10:11:15 PM UTC 24 Aug 23 10:11:18 PM UTC 24 206814135 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.3297437541 Aug 23 10:10:41 PM UTC 24 Aug 23 10:11:19 PM UTC 24 11268822151 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.2072975973 Aug 23 10:11:13 PM UTC 24 Aug 23 10:11:21 PM UTC 24 70802119 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.415162287 Aug 23 10:10:59 PM UTC 24 Aug 23 10:11:21 PM UTC 24 8637847699 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.2475578267 Aug 23 10:09:38 PM UTC 24 Aug 23 10:11:26 PM UTC 24 18331760613 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.3041969945 Aug 23 10:11:17 PM UTC 24 Aug 23 10:11:27 PM UTC 24 373544869 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.3405073273 Aug 23 10:11:22 PM UTC 24 Aug 23 10:11:27 PM UTC 24 115628960 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.1891092105 Aug 23 10:12:17 PM UTC 24 Aug 23 10:12:33 PM UTC 24 859916783 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.3038096697 Aug 23 10:11:18 PM UTC 24 Aug 23 10:11:28 PM UTC 24 939717946 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.3233614874 Aug 23 10:10:53 PM UTC 24 Aug 23 10:11:29 PM UTC 24 2522888057 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_errors.1364231842 Aug 23 10:11:15 PM UTC 24 Aug 23 10:11:30 PM UTC 24 1297678116 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.3578993378 Aug 23 10:11:12 PM UTC 24 Aug 23 10:11:30 PM UTC 24 584354662 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.706691444 Aug 23 10:11:26 PM UTC 24 Aug 23 10:11:32 PM UTC 24 824957798 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.1425987432 Aug 23 10:11:30 PM UTC 24 Aug 23 10:11:32 PM UTC 24 61075486 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.1533737853 Aug 23 10:11:30 PM UTC 24 Aug 23 10:11:32 PM UTC 24 29186548 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.3462887063 Aug 23 10:11:20 PM UTC 24 Aug 23 10:11:34 PM UTC 24 1669259037 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1521973165 Aug 23 10:11:32 PM UTC 24 Aug 23 10:11:34 PM UTC 24 39663299 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.1768175642 Aug 23 10:11:34 PM UTC 24 Aug 23 10:11:38 PM UTC 24 410134320 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.1037027702 Aug 23 10:11:28 PM UTC 24 Aug 23 10:11:39 PM UTC 24 3217568905 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.1976581178 Aug 23 10:11:29 PM UTC 24 Aug 23 10:11:39 PM UTC 24 587194773 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.1642718641 Aug 23 10:12:07 PM UTC 24 Aug 23 10:12:33 PM UTC 24 5872752634 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.1425132791 Aug 23 10:11:28 PM UTC 24 Aug 23 10:11:41 PM UTC 24 271495386 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.2991292100 Aug 23 10:11:33 PM UTC 24 Aug 23 10:11:42 PM UTC 24 58171422 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.3782879884 Aug 23 10:11:40 PM UTC 24 Aug 23 10:11:47 PM UTC 24 931440509 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.3799598518 Aug 23 10:10:59 PM UTC 24 Aug 23 10:11:49 PM UTC 24 2885632204 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_errors.1702263653 Aug 23 10:11:34 PM UTC 24 Aug 23 10:11:49 PM UTC 24 1524237486 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.2560458239 Aug 23 10:11:19 PM UTC 24 Aug 23 10:11:51 PM UTC 24 8019718991 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.2712932771 Aug 23 10:11:40 PM UTC 24 Aug 23 10:11:51 PM UTC 24 4962683283 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.229867579 Aug 23 10:11:42 PM UTC 24 Aug 23 10:11:52 PM UTC 24 565418544 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.3701165283 Aug 23 10:10:41 PM UTC 24 Aug 23 10:11:56 PM UTC 24 18787470603 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.2091872752 Aug 23 10:11:50 PM UTC 24 Aug 23 10:11:56 PM UTC 24 185528158 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.124586046 Aug 23 10:11:48 PM UTC 24 Aug 23 10:11:57 PM UTC 24 317362240 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.425403075 Aug 23 10:11:42 PM UTC 24 Aug 23 10:11:58 PM UTC 24 1683422944 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.1253770244 Aug 23 10:11:57 PM UTC 24 Aug 23 10:11:59 PM UTC 24 51343756 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.399104276 Aug 23 10:11:58 PM UTC 24 Aug 23 10:12:00 PM UTC 24 14274382 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.203189688 Aug 23 10:11:51 PM UTC 24 Aug 23 10:12:00 PM UTC 24 492022914 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.612444363 Aug 23 10:11:57 PM UTC 24 Aug 23 10:12:01 PM UTC 24 65931110 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.242761384 Aug 23 10:11:32 PM UTC 24 Aug 23 10:12:03 PM UTC 24 202290584 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.2279208068 Aug 23 10:12:00 PM UTC 24 Aug 23 10:12:04 PM UTC 24 297337073 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.1143633701 Aug 23 10:12:01 PM UTC 24 Aug 23 10:12:05 PM UTC 24 223241463 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.2932991935 Aug 23 10:11:49 PM UTC 24 Aug 23 10:12:06 PM UTC 24 392959766 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.4012261881 Aug 23 10:12:02 PM UTC 24 Aug 23 10:12:06 PM UTC 24 677813133 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.1904859082 Aug 23 10:12:01 PM UTC 24 Aug 23 10:12:09 PM UTC 24 322299516 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.1489527564 Aug 23 10:11:22 PM UTC 24 Aug 23 10:12:09 PM UTC 24 13361120209 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.3839383275 Aug 23 10:10:27 PM UTC 24 Aug 23 10:12:10 PM UTC 24 17107510319 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.4179994856 Aug 23 10:11:43 PM UTC 24 Aug 23 10:12:10 PM UTC 24 20528102330 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.523134560 Aug 23 10:12:05 PM UTC 24 Aug 23 10:12:11 PM UTC 24 298679344 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.2523699627 Aug 23 10:11:52 PM UTC 24 Aug 23 10:12:13 PM UTC 24 531812325 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.2977884716 Aug 23 10:11:08 PM UTC 24 Aug 23 10:12:14 PM UTC 24 1732120163 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_errors.2865621507 Aug 23 10:12:01 PM UTC 24 Aug 23 10:12:15 PM UTC 24 364746454 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.988181086 Aug 23 10:12:13 PM UTC 24 Aug 23 10:12:16 PM UTC 24 26883305 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.3274863845 Aug 23 10:12:07 PM UTC 24 Aug 23 10:12:17 PM UTC 24 820138676 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.4068453726 Aug 23 10:12:15 PM UTC 24 Aug 23 10:12:18 PM UTC 24 247203716 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3589656103 Aug 23 10:12:17 PM UTC 24 Aug 23 10:12:18 PM UTC 24 108411519 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.3360066062 Aug 23 10:12:10 PM UTC 24 Aug 23 10:12:19 PM UTC 24 1924042470 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.2423995132 Aug 23 10:11:59 PM UTC 24 Aug 23 10:12:20 PM UTC 24 2926492272 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.4049806112 Aug 23 10:12:05 PM UTC 24 Aug 23 10:12:21 PM UTC 24 1984930230 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.430482569 Aug 23 10:12:11 PM UTC 24 Aug 23 10:12:22 PM UTC 24 642484718 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.1730306703 Aug 23 10:12:19 PM UTC 24 Aug 23 10:12:23 PM UTC 24 492582187 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.3908630540 Aug 23 10:12:11 PM UTC 24 Aug 23 10:12:25 PM UTC 24 1645249621 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.573861091 Aug 23 10:12:32 PM UTC 24 Aug 23 10:12:34 PM UTC 24 19781283 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.2691177250 Aug 23 10:11:03 PM UTC 24 Aug 23 10:12:26 PM UTC 24 3680211037 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.2161865066 Aug 23 10:12:18 PM UTC 24 Aug 23 10:12:27 PM UTC 24 290483855 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.449690334 Aug 23 10:12:20 PM UTC 24 Aug 23 10:12:28 PM UTC 24 269554395 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.3153106571 Aug 23 10:12:19 PM UTC 24 Aug 23 10:12:31 PM UTC 24 1320708186 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_errors.2216680159 Aug 23 10:12:19 PM UTC 24 Aug 23 10:12:32 PM UTC 24 1141243612 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3792374404 Aug 23 10:12:33 PM UTC 24 Aug 23 10:12:36 PM UTC 24 12674019 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.989165688 Aug 23 10:12:25 PM UTC 24 Aug 23 10:12:36 PM UTC 24 480831026 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.3814064585 Aug 23 10:12:27 PM UTC 24 Aug 23 10:12:36 PM UTC 24 1458422458 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.200532910 Aug 23 10:12:26 PM UTC 24 Aug 23 10:12:36 PM UTC 24 1448192866 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.2105836158 Aug 23 10:12:33 PM UTC 24 Aug 23 10:12:36 PM UTC 24 34681901 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.3361330845 Aug 23 10:12:27 PM UTC 24 Aug 23 10:12:37 PM UTC 24 494714869 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.783068978 Aug 23 10:12:21 PM UTC 24 Aug 23 10:12:37 PM UTC 24 1376638252 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.519369839 Aug 23 10:12:36 PM UTC 24 Aug 23 10:12:39 PM UTC 24 67862101 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.2371072508 Aug 23 10:12:37 PM UTC 24 Aug 23 10:12:44 PM UTC 24 1890269536 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.1534140996 Aug 23 10:12:38 PM UTC 24 Aug 23 10:12:45 PM UTC 24 3256847163 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.2824391622 Aug 23 10:12:22 PM UTC 24 Aug 23 10:12:47 PM UTC 24 1012501838 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.2049104178 Aug 23 10:12:37 PM UTC 24 Aug 23 10:12:48 PM UTC 24 545066081 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_errors.3300243151 Aug 23 10:12:37 PM UTC 24 Aug 23 10:12:48 PM UTC 24 590213399 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.909719129 Aug 23 10:12:36 PM UTC 24 Aug 23 10:12:49 PM UTC 24 88241412 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.2694543576 Aug 23 10:12:40 PM UTC 24 Aug 23 10:12:50 PM UTC 24 670321096 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.664079527 Aug 23 10:12:37 PM UTC 24 Aug 23 10:12:51 PM UTC 24 676221414 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.2646379029 Aug 23 10:12:50 PM UTC 24 Aug 23 10:12:52 PM UTC 24 15074477 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.3718519744 Aug 23 10:12:51 PM UTC 24 Aug 23 10:12:54 PM UTC 24 30188382 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.4031533314 Aug 23 10:12:45 PM UTC 24 Aug 23 10:12:54 PM UTC 24 428758135 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3852650708 Aug 23 10:12:52 PM UTC 24 Aug 23 10:12:54 PM UTC 24 11013543 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.1465946750 Aug 23 10:12:25 PM UTC 24 Aug 23 10:12:54 PM UTC 24 5472644200 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.319215731 Aug 23 10:12:04 PM UTC 24 Aug 23 10:12:56 PM UTC 24 17764217113 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.3296247005 Aug 23 10:12:34 PM UTC 24 Aug 23 10:12:57 PM UTC 24 1104592576 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.2799670068 Aug 23 10:12:54 PM UTC 24 Aug 23 10:12:58 PM UTC 24 40319409 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.5549668 Aug 23 10:12:48 PM UTC 24 Aug 23 10:12:59 PM UTC 24 717588939 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.2546580155 Aug 23 10:12:53 PM UTC 24 Aug 23 10:13:01 PM UTC 24 260671773 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.2631543491 Aug 23 10:12:44 PM UTC 24 Aug 23 10:13:01 PM UTC 24 1876974573 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_errors.2285734015 Aug 23 10:12:54 PM UTC 24 Aug 23 10:13:03 PM UTC 24 1011659849 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.657136201 Aug 23 10:12:59 PM UTC 24 Aug 23 10:13:04 PM UTC 24 419375425 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.4002857273 Aug 23 10:12:54 PM UTC 24 Aug 23 10:13:04 PM UTC 24 956124062 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.1549784821 Aug 23 10:12:37 PM UTC 24 Aug 23 10:13:05 PM UTC 24 1911073177 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.3419033397 Aug 23 10:12:55 PM UTC 24 Aug 23 10:13:08 PM UTC 24 513515976 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.3790129496 Aug 23 10:12:58 PM UTC 24 Aug 23 10:13:11 PM UTC 24 895402622 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.4254554808 Aug 23 10:13:02 PM UTC 24 Aug 23 10:13:11 PM UTC 24 353714445 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.1610145577 Aug 23 10:13:09 PM UTC 24 Aug 23 10:13:11 PM UTC 24 33836112 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.3055132323 Aug 23 10:12:21 PM UTC 24 Aug 23 10:13:12 PM UTC 24 3716491491 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.1996369663 Aug 23 10:13:04 PM UTC 24 Aug 23 10:13:12 PM UTC 24 1528285854 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.4241592678 Aug 23 10:13:12 PM UTC 24 Aug 23 10:13:13 PM UTC 24 14254240 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.2540579188 Aug 23 10:13:12 PM UTC 24 Aug 23 10:13:14 PM UTC 24 26621776 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.1486287444 Aug 23 10:13:13 PM UTC 24 Aug 23 10:13:16 PM UTC 24 68512076 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.1444433567 Aug 23 10:13:05 PM UTC 24 Aug 23 10:13:17 PM UTC 24 441324629 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.4018733604 Aug 23 10:13:02 PM UTC 24 Aug 23 10:13:18 PM UTC 24 1661695295 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.2624013872 Aug 23 10:13:13 PM UTC 24 Aug 23 10:13:21 PM UTC 24 107203595 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.50182425 Aug 23 10:12:53 PM UTC 24 Aug 23 10:13:22 PM UTC 24 235845239 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_errors.3385524523 Aug 23 10:13:14 PM UTC 24 Aug 23 10:13:23 PM UTC 24 456631708 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.519149512 Aug 23 10:10:01 PM UTC 24 Aug 23 10:13:23 PM UTC 24 5631828598 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.569305914 Aug 23 10:13:17 PM UTC 24 Aug 23 10:13:24 PM UTC 24 406603818 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.3529033760 Aug 23 10:13:14 PM UTC 24 Aug 23 10:13:24 PM UTC 24 251142194 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.3583564545 Aug 23 10:13:21 PM UTC 24 Aug 23 10:13:28 PM UTC 24 690226141 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.1791459823 Aug 23 10:12:38 PM UTC 24 Aug 23 10:13:30 PM UTC 24 1774709288 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.923245687 Aug 23 10:13:00 PM UTC 24 Aug 23 10:13:30 PM UTC 24 8222725347 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.1429420861 Aug 23 10:13:18 PM UTC 24 Aug 23 10:13:32 PM UTC 24 2439596533 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.4021570526 Aug 23 10:13:13 PM UTC 24 Aug 23 10:13:33 PM UTC 24 1779856201 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.3355241817 Aug 23 10:13:24 PM UTC 24 Aug 23 10:13:33 PM UTC 24 1708759463 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.449442446 Aug 23 10:13:31 PM UTC 24 Aug 23 10:13:34 PM UTC 24 21787097 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.2553151647 Aug 23 10:13:25 PM UTC 24 Aug 23 10:13:34 PM UTC 24 276828060 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.580171914 Aug 23 10:13:24 PM UTC 24 Aug 23 10:13:35 PM UTC 24 436450812 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1799530035 Aug 23 10:13:34 PM UTC 24 Aug 23 10:13:35 PM UTC 24 51553562 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.209552140 Aug 23 10:13:32 PM UTC 24 Aug 23 10:13:36 PM UTC 24 38866970 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.1808954894 Aug 23 10:13:24 PM UTC 24 Aug 23 10:13:39 PM UTC 24 3815466679 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.2746120635 Aug 23 10:13:35 PM UTC 24 Aug 23 10:13:39 PM UTC 24 217427269 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.316235598 Aug 23 10:13:35 PM UTC 24 Aug 23 10:13:43 PM UTC 24 343995706 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.379047020 Aug 23 10:12:11 PM UTC 24 Aug 23 10:13:43 PM UTC 24 73863396842 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_errors.3832067820 Aug 23 10:13:36 PM UTC 24 Aug 23 10:13:46 PM UTC 24 280675740 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.4149278154 Aug 23 10:13:37 PM UTC 24 Aug 23 10:13:46 PM UTC 24 573174331 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.647577974 Aug 23 10:11:29 PM UTC 24 Aug 23 10:13:47 PM UTC 24 17125658516 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.4020340426 Aug 23 10:12:57 PM UTC 24 Aug 23 10:13:47 PM UTC 24 1464988287 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.2036249405 Aug 23 10:13:40 PM UTC 24 Aug 23 10:13:49 PM UTC 24 424249958 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.4037905622 Aug 23 10:13:36 PM UTC 24 Aug 23 10:13:51 PM UTC 24 2653801320 ps
T501 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.171895804 Aug 23 10:13:48 PM UTC 24 Aug 23 10:13:54 PM UTC 24 758750769 ps
T502 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.3301136244 Aug 23 10:13:44 PM UTC 24 Aug 23 10:13:55 PM UTC 24 4666947810 ps
T503 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.3832323842 Aug 23 10:13:55 PM UTC 24 Aug 23 10:13:57 PM UTC 24 37008047 ps
T504 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.3014174173 Aug 23 10:13:35 PM UTC 24 Aug 23 10:13:58 PM UTC 24 1054977235 ps
T505 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.3868991578 Aug 23 10:13:55 PM UTC 24 Aug 23 10:13:59 PM UTC 24 147886627 ps
T506 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.1569607364 Aug 23 10:13:47 PM UTC 24 Aug 23 10:14:00 PM UTC 24 1044759401 ps
T507 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.2923828023 Aug 23 10:13:47 PM UTC 24 Aug 23 10:14:00 PM UTC 24 1547523872 ps
T508 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.3612645702 Aug 23 10:13:48 PM UTC 24 Aug 23 10:14:00 PM UTC 24 844183494 ps
T509 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1101592079 Aug 23 10:13:59 PM UTC 24 Aug 23 10:14:00 PM UTC 24 14761792 ps
T510 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.1935914360 Aug 23 10:14:01 PM UTC 24 Aug 23 10:14:03 PM UTC 24 151866490 ps
T511 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.3115580097 Aug 23 10:13:23 PM UTC 24 Aug 23 10:14:09 PM UTC 24 1918435378 ps
T512 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.1930814979 Aug 23 10:14:00 PM UTC 24 Aug 23 10:14:04 PM UTC 24 247601461 ps
T513 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.449127120 Aug 23 10:14:01 PM UTC 24 Aug 23 10:14:08 PM UTC 24 204863465 ps
T514 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.78795167 Aug 23 10:14:01 PM UTC 24 Aug 23 10:14:10 PM UTC 24 1481014223 ps
T515 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.148653092 Aug 23 10:14:05 PM UTC 24 Aug 23 10:14:12 PM UTC 24 860994567 ps
T516 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_errors.3721028730 Aug 23 10:14:01 PM UTC 24 Aug 23 10:14:13 PM UTC 24 2353147542 ps
T517 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.2380141086 Aug 23 10:08:52 PM UTC 24 Aug 23 10:14:14 PM UTC 24 80830254275 ps
T518 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.3361726423 Aug 23 10:14:12 PM UTC 24 Aug 23 10:14:14 PM UTC 24 26336277 ps
T519 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.4056390779 Aug 23 10:14:14 PM UTC 24 Aug 23 10:14:16 PM UTC 24 66397032 ps
T520 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3599161847 Aug 23 10:14:15 PM UTC 24 Aug 23 10:14:16 PM UTC 24 40652616 ps
T521 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.3659792936 Aug 23 10:14:04 PM UTC 24 Aug 23 10:14:18 PM UTC 24 1437212319 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1671878989 Aug 23 10:13:30 PM UTC 24 Aug 23 10:14:20 PM UTC 24 4134177495 ps
T522 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.2823129847 Aug 23 10:14:17 PM UTC 24 Aug 23 10:14:20 PM UTC 24 89807687 ps
T523 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.4129006597 Aug 23 10:14:08 PM UTC 24 Aug 23 10:14:22 PM UTC 24 1720507977 ps
T524 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.706509392 Aug 23 10:13:40 PM UTC 24 Aug 23 10:14:23 PM UTC 24 8693460700 ps
T525 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.669045067 Aug 23 10:14:17 PM UTC 24 Aug 23 10:14:25 PM UTC 24 295036983 ps
T526 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.700819046 Aug 23 10:13:05 PM UTC 24 Aug 23 10:14:25 PM UTC 24 1722818466 ps
T527 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.2449651225 Aug 23 10:13:59 PM UTC 24 Aug 23 10:14:25 PM UTC 24 749686683 ps
T528 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.2391342017 Aug 23 10:14:21 PM UTC 24 Aug 23 10:14:25 PM UTC 24 84783245 ps
T529 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.3947354620 Aug 23 10:14:26 PM UTC 24 Aug 23 10:14:28 PM UTC 24 34844263 ps
T530 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_errors.2430421128 Aug 23 10:14:18 PM UTC 24 Aug 23 10:14:29 PM UTC 24 705792538 ps
T531 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.4217321132 Aug 23 10:12:49 PM UTC 24 Aug 23 10:14:30 PM UTC 24 5113862469 ps
T532 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.2813177021 Aug 23 10:14:21 PM UTC 24 Aug 23 10:14:31 PM UTC 24 243564394 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.2103134787 Aug 23 10:13:05 PM UTC 24 Aug 23 10:14:31 PM UTC 24 2606048903 ps
T533 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.53529485 Aug 23 10:14:23 PM UTC 24 Aug 23 10:14:31 PM UTC 24 1250289312 ps
T534 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.2462168318 Aug 23 10:14:29 PM UTC 24 Aug 23 10:14:32 PM UTC 24 25553695 ps
T535 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1953810616 Aug 23 10:14:30 PM UTC 24 Aug 23 10:14:32 PM UTC 24 15225997 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.1294269522 Aug 23 10:07:49 PM UTC 24 Aug 23 10:14:32 PM UTC 24 50898797766 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.2824288811 Aug 23 10:13:44 PM UTC 24 Aug 23 10:14:34 PM UTC 24 1932684118 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.2951808582 Aug 23 10:14:33 PM UTC 24 Aug 23 10:14:35 PM UTC 24 30261934 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.3759630823 Aug 23 10:14:26 PM UTC 24 Aug 23 10:14:36 PM UTC 24 1239153413 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.3820551135 Aug 23 10:14:23 PM UTC 24 Aug 23 10:14:36 PM UTC 24 604146259 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.1759062451 Aug 23 10:14:15 PM UTC 24 Aug 23 10:14:37 PM UTC 24 172187713 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.3378708362 Aug 23 10:13:17 PM UTC 24 Aug 23 10:14:38 PM UTC 24 5203919589 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_errors.659518113 Aug 23 10:15:10 PM UTC 24 Aug 23 10:15:23 PM UTC 24 569229743 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.3202020951 Aug 23 10:14:31 PM UTC 24 Aug 23 10:14:40 PM UTC 24 1338898268 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.1010456193 Aug 23 10:14:39 PM UTC 24 Aug 23 10:14:41 PM UTC 24 56410360 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.198577180 Aug 23 10:14:33 PM UTC 24 Aug 23 10:14:42 PM UTC 24 1858627274 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.2068952538 Aug 23 10:14:39 PM UTC 24 Aug 23 10:14:42 PM UTC 24 102560267 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.2439147372 Aug 23 10:14:33 PM UTC 24 Aug 23 10:14:42 PM UTC 24 664223483 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.200083481 Aug 23 10:14:41 PM UTC 24 Aug 23 10:14:43 PM UTC 24 53526979 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.2447460010 Aug 23 10:14:34 PM UTC 24 Aug 23 10:14:44 PM UTC 24 964130733 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.1652689448 Aug 23 10:10:47 PM UTC 24 Aug 23 10:14:45 PM UTC 24 33965638093 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_errors.845174734 Aug 23 10:14:33 PM UTC 24 Aug 23 10:14:45 PM UTC 24 397742189 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.4121498750 Aug 23 10:14:54 PM UTC 24 Aug 23 10:15:24 PM UTC 24 435136755 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.3501464541 Aug 23 10:14:35 PM UTC 24 Aug 23 10:14:46 PM UTC 24 1107927774 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.4078416687 Aug 23 10:14:43 PM UTC 24 Aug 23 10:14:47 PM UTC 24 102565313 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.219054981 Aug 23 10:14:43 PM UTC 24 Aug 23 10:14:47 PM UTC 24 58974252 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.1905021683 Aug 23 10:14:36 PM UTC 24 Aug 23 10:14:48 PM UTC 24 2411513763 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.3580888718 Aug 23 10:14:49 PM UTC 24 Aug 23 10:14:51 PM UTC 24 19392974 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.2932500725 Aug 23 10:14:44 PM UTC 24 Aug 23 10:14:53 PM UTC 24 789960198 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.4167348252 Aug 23 10:14:45 PM UTC 24 Aug 23 10:14:53 PM UTC 24 1202916543 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.522893998 Aug 23 10:14:53 PM UTC 24 Aug 23 10:14:55 PM UTC 24 40248958 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.953396454 Aug 23 10:14:52 PM UTC 24 Aug 23 10:14:55 PM UTC 24 127411102 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.4211497503 Aug 23 10:14:43 PM UTC 24 Aug 23 10:14:55 PM UTC 24 367573300 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.2741281195 Aug 23 10:14:45 PM UTC 24 Aug 23 10:14:56 PM UTC 24 1234064951 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_errors.2469958170 Aug 23 10:14:43 PM UTC 24 Aug 23 10:14:57 PM UTC 24 1185038493 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.4090039877 Aug 23 10:15:11 PM UTC 24 Aug 23 10:15:22 PM UTC 24 386874228 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.2427520204 Aug 23 10:14:47 PM UTC 24 Aug 23 10:14:58 PM UTC 24 2036775702 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.2123364037 Aug 23 10:14:55 PM UTC 24 Aug 23 10:14:58 PM UTC 24 156824145 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.3607673937 Aug 23 10:14:30 PM UTC 24 Aug 23 10:14:58 PM UTC 24 592502581 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.3661303794 Aug 23 10:14:55 PM UTC 24 Aug 23 10:14:59 PM UTC 24 69864237 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.2621498613 Aug 23 10:14:59 PM UTC 24 Aug 23 10:15:03 PM UTC 24 585211172 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_errors.3190476055 Aug 23 10:14:56 PM UTC 24 Aug 23 10:15:04 PM UTC 24 1163944523 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.1307524133 Aug 23 10:15:03 PM UTC 24 Aug 23 10:15:05 PM UTC 24 16523793 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.2246078314 Aug 23 10:15:05 PM UTC 24 Aug 23 10:15:08 PM UTC 24 58295895 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.600773349 Aug 23 10:15:06 PM UTC 24 Aug 23 10:15:08 PM UTC 24 14962106 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.601185736 Aug 23 10:15:20 PM UTC 24 Aug 23 10:15:22 PM UTC 24 190204926 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.819197724 Aug 23 10:14:59 PM UTC 24 Aug 23 10:15:09 PM UTC 24 266412762 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.96620075 Aug 23 10:14:42 PM UTC 24 Aug 23 10:15:09 PM UTC 24 668646194 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.1195250302 Aug 23 10:14:59 PM UTC 24 Aug 23 10:15:10 PM UTC 24 455367439 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.1867150729 Aug 23 10:14:57 PM UTC 24 Aug 23 10:15:10 PM UTC 24 1460430185 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.1075621550 Aug 23 10:14:59 PM UTC 24 Aug 23 10:15:11 PM UTC 24 347604755 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.4039836582 Aug 23 10:15:10 PM UTC 24 Aug 23 10:15:13 PM UTC 24 193523011 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.2832305203 Aug 23 10:13:29 PM UTC 24 Aug 23 10:15:16 PM UTC 24 10101128190 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.3993221487 Aug 23 10:15:17 PM UTC 24 Aug 23 10:15:19 PM UTC 24 33444319 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.888616732 Aug 23 10:15:20 PM UTC 24 Aug 23 10:15:23 PM UTC 24 458104659 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.1775367120 Aug 23 10:15:10 PM UTC 24 Aug 23 10:15:19 PM UTC 24 75017307 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.2279140991 Aug 23 10:15:11 PM UTC 24 Aug 23 10:15:20 PM UTC 24 1377776336 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.3564754225 Aug 23 10:12:28 PM UTC 24 Aug 23 10:15:21 PM UTC 24 5954831420 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.4265364949 Aug 23 10:15:12 PM UTC 24 Aug 23 10:15:24 PM UTC 24 340948766 ps
T588 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.2209966981 Aug 23 10:15:13 PM UTC 24 Aug 23 10:15:23 PM UTC 24 269360227 ps
T589 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.1845029486 Aug 23 10:15:22 PM UTC 24 Aug 23 10:15:25 PM UTC 24 26730227 ps
T590 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.2755692097 Aug 23 10:15:21 PM UTC 24 Aug 23 10:15:28 PM UTC 24 60636487 ps
T591 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.4183107611 Aug 23 10:15:08 PM UTC 24 Aug 23 10:15:29 PM UTC 24 958534023 ps
T592 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.2280047421 Aug 23 10:15:11 PM UTC 24 Aug 23 10:15:31 PM UTC 24 524305624 ps
T593 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.2571217682 Aug 23 10:15:22 PM UTC 24 Aug 23 10:15:31 PM UTC 24 316311081 ps
T594 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.4069994527 Aug 23 10:15:29 PM UTC 24 Aug 23 10:15:31 PM UTC 24 20416064 ps
T595 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.3921655561 Aug 23 10:15:24 PM UTC 24 Aug 23 10:15:33 PM UTC 24 2352998722 ps
T596 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.4081528310 Aug 23 10:15:31 PM UTC 24 Aug 23 10:15:33 PM UTC 24 13979794 ps
T597 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_errors.2250654359 Aug 23 10:15:22 PM UTC 24 Aug 23 10:15:34 PM UTC 24 1180060340 ps
T598 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.3552592718 Aug 23 10:15:25 PM UTC 24 Aug 23 10:15:34 PM UTC 24 560928811 ps
T599 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.1133640562 Aug 23 10:15:24 PM UTC 24 Aug 23 10:15:34 PM UTC 24 4013476928 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.3450130779 Aug 23 10:15:24 PM UTC 24 Aug 23 10:15:35 PM UTC 24 748724359 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.127663510 Aug 23 10:15:34 PM UTC 24 Aug 23 10:15:38 PM UTC 24 72895398 ps
T602 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.2167967088 Aug 23 10:15:35 PM UTC 24 Aug 23 10:15:38 PM UTC 24 69671011 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.1987672722 Aug 23 10:15:30 PM UTC 24 Aug 23 10:15:40 PM UTC 24 165604855 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.414663545 Aug 23 10:15:33 PM UTC 24 Aug 23 10:15:41 PM UTC 24 277632763 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.4020207632 Aug 23 10:15:41 PM UTC 24 Aug 23 10:15:43 PM UTC 24 55642561 ps
T605 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.802899039 Aug 23 10:15:36 PM UTC 24 Aug 23 10:15:43 PM UTC 24 234410423 ps
T606 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.2103721903 Aug 23 10:15:35 PM UTC 24 Aug 23 10:15:43 PM UTC 24 179278518 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.3707112323 Aug 23 10:15:35 PM UTC 24 Aug 23 10:15:44 PM UTC 24 180985005 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.702234352 Aug 23 10:15:20 PM UTC 24 Aug 23 10:15:45 PM UTC 24 305324719 ps
T609 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.892571601 Aug 23 10:15:44 PM UTC 24 Aug 23 10:15:46 PM UTC 24 154025217 ps
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