Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	703009	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

888025

1

T1

3

T2

5

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1307743	1			T1	2		T2	35		T3	2
values[0x0]	140905	1			T2	3		T13	1		T14	2
values[0x1]	142386	1			T1	1		T2	5		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	555650	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1035384

1

T1

3

T2

17

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5384	1			T20	1		T27	5		T23	20
valid_sources[0x01]	4732	1			T20	3		T32	1		T24	1
valid_sources[0x02]	4789	1			T27	1		T23	26		T26	2
valid_sources[0x03]	4730	1			T15	1		T5	2		T20	1
valid_sources[0x04]	4961	1			T15	2		T27	4		T23	14
valid_sources[0x05]	4772	1			T15	1		T20	4		T27	3
valid_sources[0x06]	6901	1			T20	1		T27	3		T23	11
valid_sources[0x07]	4997	1			T23	18		T25	11		T31	8
valid_sources[0x08]	4395	1			T5	2		T20	1		T25	3
valid_sources[0x09]	5116	1			T16	2		T6	155		T20	1
valid_sources[0x0a]	5112	1			T23	3		T31	4		T26	8
valid_sources[0x0b]	6143	1			T16	1		T20	1		T23	19
valid_sources[0x0c]	4899	1			T80	1		T23	39		T24	2
valid_sources[0x0d]	9456	1			T80	1		T27	1		T23	4
valid_sources[0x0e]	7376	1			T16	2		T20	3		T27	3
valid_sources[0x0f]	8822	1			T20	1		T27	5		T23	27
valid_sources[0x10]	4939	1			T80	1		T20	2		T23	9
valid_sources[0x11]	5051	1			T20	1		T27	4		T23	3
valid_sources[0x12]	4736	1			T5	2		T25	4		T9	3
valid_sources[0x13]	5361	1			T5	2		T20	1		T23	1
valid_sources[0x14]	6635	1			T20	1		T27	1		T25	4
valid_sources[0x15]	4831	1			T15	1		T5	4		T25	14
valid_sources[0x16]	4725	1			T16	1		T27	4		T24	1
valid_sources[0x17]	4494	1			T16	4		T24	1		T25	6
valid_sources[0x18]	10937	1			T20	5		T23	22		T26	20
valid_sources[0x19]	4829	1			T27	1		T9	1		T31	2
valid_sources[0x1a]	5116	1			T20	2		T23	5		T24	2
valid_sources[0x1b]	6385	1			T5	2		T20	3		T27	1
valid_sources[0x1c]	7707	1			T15	2		T23	7		T25	15
valid_sources[0x1d]	4791	1			T23	11		T26	8		T10	6
valid_sources[0x1e]	4495	1			T16	1		T23	1		T24	1
valid_sources[0x1f]	4947	1			T80	2		T27	2		T23	10
valid_sources[0x20]	5000	1			T16	1		T20	2		T27	3
valid_sources[0x21]	5414	1			T80	3		T32	1		T23	2
valid_sources[0x22]	6486	1			T20	2		T27	3		T29	303
valid_sources[0x23]	4769	1			T23	4		T31	1		T26	1
valid_sources[0x24]	4870	1			T15	2		T20	2		T27	1
valid_sources[0x25]	37155	1			T27	2		T23	2		T25	5
valid_sources[0x26]	7736	1			T15	1		T20	2		T27	5
valid_sources[0x27]	4947	1			T16	1		T5	2		T20	3
valid_sources[0x28]	4935	1			T5	1		T27	1		T31	4
valid_sources[0x29]	4742	1			T23	26		T54	2		T31	2
valid_sources[0x2a]	4846	1			T20	5		T23	14		T25	5
valid_sources[0x2b]	5017	1			T15	2		T20	1		T23	4
valid_sources[0x2c]	4950	1			T5	1		T27	1		T32	2
valid_sources[0x2d]	6072	1			T5	1		T20	8		T32	1
valid_sources[0x2e]	5041	1			T15	1		T5	1		T27	3
valid_sources[0x2f]	6399	1			T23	8		T25	8		T54	1
valid_sources[0x30]	5241	1			T20	3		T27	1		T23	21
valid_sources[0x31]	10017	1			T16	1		T5	1		T23	3
valid_sources[0x32]	9909	1			T5	1		T23	19		T24	1
valid_sources[0x33]	19529	1			T27	2		T28	416		T23	6
valid_sources[0x34]	4991	1			T16	3		T20	1		T23	8
valid_sources[0x35]	5315	1			T16	2		T5	1		T27	3
valid_sources[0x36]	6111	1			T23	9		T86	1		T25	7
valid_sources[0x37]	4813	1			T5	3		T20	3		T25	2
valid_sources[0x38]	4955	1			T16	2		T80	1		T20	2
valid_sources[0x39]	4938	1			T23	1		T25	2		T9	1
valid_sources[0x3a]	4701	1			T23	10		T31	5		T26	33
valid_sources[0x3b]	4896	1			T15	1		T20	3		T32	1
valid_sources[0x3c]	6426	1			T16	1		T80	1		T23	3
valid_sources[0x3d]	4972	1			T15	2		T20	1		T27	2
valid_sources[0x3e]	7108	1			T23	5		T24	1		T54	1
valid_sources[0x3f]	6465	1			T15	1		T20	1		T24	1
valid_sources[0x40]	4886	1			T80	1		T25	6		T31	4
valid_sources[0x41]	7378	1			T27	2		T23	26		T24	1
valid_sources[0x42]	6962	1			T5	1		T54	1		T31	5
valid_sources[0x43]	5897	1			T16	2		T20	2		T23	3
valid_sources[0x44]	6089	1			T16	2		T5	1		T27	1
valid_sources[0x45]	4763	1			T15	1		T80	1		T5	2
valid_sources[0x46]	6088	1			T20	3		T32	1		T25	5
valid_sources[0x47]	7472	1			T27	3		T25	6		T54	1
valid_sources[0x48]	6723	1			T20	1		T27	2		T23	5
valid_sources[0x49]	7072	1			T27	2		T54	1		T31	1
valid_sources[0x4a]	4938	1			T80	2		T25	8		T9	1
valid_sources[0x4b]	5372	1			T31	1		T26	2		T39	7
valid_sources[0x4c]	4758	1			T14	6		T16	1		T5	1
valid_sources[0x4d]	4921	1			T18	20		T23	28		T31	2
valid_sources[0x4e]	7490	1			T3	1		T23	20		T25	6
valid_sources[0x4f]	5125	1			T1	3		T80	1		T20	1
valid_sources[0x50]	6839	1			T5	1		T27	1		T23	1
valid_sources[0x51]	6144	1			T16	1		T20	3		T25	16
valid_sources[0x52]	6468	1			T15	1		T16	1		T20	1
valid_sources[0x53]	4608	1			T5	1		T23	27		T24	1
valid_sources[0x54]	5878	1			T27	1		T23	10		T31	2
valid_sources[0x55]	7627	1			T23	6		T25	6		T54	1
valid_sources[0x56]	4840	1			T5	4		T20	1		T25	3
valid_sources[0x57]	5006	1			T16	1		T5	3		T20	4
valid_sources[0x58]	5851	1			T20	1		T27	4		T23	20
valid_sources[0x59]	5342	1			T3	1		T20	2		T27	4
valid_sources[0x5a]	7995	1			T20	1		T23	11		T25	4
valid_sources[0x5b]	5110	1			T20	1		T27	3		T24	1
valid_sources[0x5c]	4706	1			T5	2		T20	1		T27	3
valid_sources[0x5d]	6730	1			T15	1		T5	1		T54	2
valid_sources[0x5e]	4740	1			T15	2		T23	44		T24	1
valid_sources[0x5f]	5183	1			T5	1		T25	5		T31	2
valid_sources[0x60]	4690	1			T5	1		T20	2		T23	26
valid_sources[0x61]	4835	1			T20	2		T25	12		T54	2
valid_sources[0x62]	4628	1			T5	1		T23	4		T25	6
valid_sources[0x63]	5177	1			T31	3		T26	3		T39	6
valid_sources[0x64]	4968	1			T15	1		T20	1		T23	2
valid_sources[0x65]	4926	1			T20	2		T25	6		T54	1
valid_sources[0x66]	4891	1			T20	3		T23	5		T54	1
valid_sources[0x67]	12544	1			T5	1		T20	1		T23	15
valid_sources[0x68]	6744	1			T5	1		T25	3		T31	3
valid_sources[0x69]	5175	1			T5	1		T23	5		T46	15
valid_sources[0x6a]	4920	1			T16	2		T20	2		T23	18
valid_sources[0x6b]	4896	1			T5	1		T20	3		T23	6
valid_sources[0x6c]	6306	1			T15	2		T20	4		T23	7
valid_sources[0x6d]	4652	1			T20	1		T32	1		T24	1
valid_sources[0x6e]	4843	1			T20	1		T27	5		T31	2
valid_sources[0x6f]	4439	1			T80	1		T20	1		T25	2
valid_sources[0x70]	4721	1			T31	3		T26	25		T10	4
valid_sources[0x71]	7847	1			T20	2		T27	8		T23	3
valid_sources[0x72]	4872	1			T15	3		T54	2		T31	3
valid_sources[0x73]	4774	1			T27	4		T54	2		T26	9
valid_sources[0x74]	4986	1			T27	1		T25	25		T9	3
valid_sources[0x75]	4745	1			T15	3		T20	4		T25	10
valid_sources[0x76]	6237	1			T20	1		T23	30		T25	8
valid_sources[0x77]	4720	1			T5	1		T23	2		T54	1
valid_sources[0x78]	7024	1			T23	13		T25	5		T54	1
valid_sources[0x79]	4750	1			T19	3		T5	2		T27	1
valid_sources[0x7a]	7332	1			T15	1		T5	1		T23	24
valid_sources[0x7b]	11658	1			T14	7		T23	6		T31	8
valid_sources[0x7c]	6316	1			T5	1		T20	2		T27	3
valid_sources[0x7d]	4928	1			T27	4		T25	10		T54	1
valid_sources[0x7e]	4828	1			T54	1		T31	2		T26	24
valid_sources[0x7f]	4667	1			T16	2		T23	27		T25	3
valid_sources[0x80]	5105	1			T27	3		T23	1		T25	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

644697

1

T1

2

T3

1

T13

1

values[0x0]

all_enables

biggest_size

121910

1

T2

2

T13

1

T14

2

values[0x1]

all_enables

biggest_size

121418

1

T1

1

T2

3

T14

3