Group : dv_base_reg_pkg::mubi_cov#(8,32'h00000096,32'h00000069)::mubi_cg
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Group : dv_base_reg_pkg::mubi_cov#(8,32'h00000096,32'h00000069)::mubi_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
70.00 70.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex 70.00 1 100 1 64 64




Group Instance : mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
70.00 1 100 1 64 64




Summary for Group Instance mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 3 7 70.00


Variables for Group Instance mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 10 3 7 70.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 3 7 70.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[6] 0 1 1
others[7] 0 1 1
false 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 2305 1 T9 8 T10 12 T11 150
others[1] 1 1 T3 1 - - - -
others[2] 1 1 T256 1 - - - -
others[3] 2 1 T19 1 T86 1 - -
others[4] 2 1 T13 1 T141 1 - -
others[5] 1 1 T257 1 - - - -
true 40584 1 T1 1 T2 1 T14 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%