Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	57165167	14343	0	0
claim_transition_if_regwen_rd_A	57165167	1815	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57165167	14343	0	0
T109	179936	6	0	0
T110	0	3	0	0
T111	0	5	0	0
T145	0	4	0	0
T146	0	7	0	0
T185	0	21	0	0
T186	0	2	0	0
T187	0	12	0	0
T188	0	2	0	0
T189	0	2	0	0
T190	43697	0	0	0
T191	24156	0	0	0
T192	25520	0	0	0
T193	32974	0	0	0
T194	7311	0	0	0
T195	22929	0	0	0
T196	22914	0	0	0
T197	57539	0	0	0
T198	41785	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57165167	1815	0	0
T98	4255	0	0	0
T111	230678	10	0	0
T145	0	7	0	0
T188	0	12	0	0
T189	0	13	0	0
T199	0	6	0	0
T200	0	11	0	0
T201	0	442	0	0
T202	0	29	0	0
T203	0	465	0	0
T204	0	48	0	0
T205	829	0	0	0
T206	43321	0	0	0
T207	2282	0	0	0
T208	35027	0	0	0
T209	41258	0	0	0
T210	6910	0	0	0
T211	3785	0	0	0
T212	7126	0	0	0