Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	831732	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1020945

1

T1

5

T3

463

T4

133

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1558320	1			T1	53		T2	2		T3	755
values[0x0]	146903	1			T1	4		T3	52		T4	55
values[0x1]	147454	1			T1	4		T2	1		T3	65

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	657738	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1194939

1

T1

21

T2

1

T3

546

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5730	1			T5	5		T15	7		T19	4
valid_sources[0x01]	7325	1			T5	4		T15	4		T8	3
valid_sources[0x02]	18562	1			T5	2		T15	6		T19	6
valid_sources[0x03]	6049	1			T1	1		T5	2		T15	5
valid_sources[0x04]	5703	1			T3	3		T15	2		T19	1
valid_sources[0x05]	5828	1			T1	1		T3	9		T5	3
valid_sources[0x06]	6234	1			T3	14		T5	1		T15	5
valid_sources[0x07]	7082	1			T3	5		T5	3		T15	8
valid_sources[0x08]	6124	1			T3	12		T5	2		T15	9
valid_sources[0x09]	6751	1			T5	4		T15	9		T19	1
valid_sources[0x0a]	8146	1			T15	7		T8	3		T16	1
valid_sources[0x0b]	9033	1			T5	4		T15	4		T7	5
valid_sources[0x0c]	5601	1			T5	1		T15	13		T8	3
valid_sources[0x0d]	5913	1			T1	1		T3	16		T5	6
valid_sources[0x0e]	7743	1			T3	5		T5	1		T19	4
valid_sources[0x0f]	6231	1			T5	1		T15	4		T19	5
valid_sources[0x10]	6460	1			T5	4		T15	6		T19	2
valid_sources[0x11]	5797	1			T5	2		T15	5		T26	19
valid_sources[0x12]	5823	1			T5	1		T15	4		T19	7
valid_sources[0x13]	6183	1			T15	4		T8	3		T19	7
valid_sources[0x14]	5991	1			T1	1		T3	5		T15	9
valid_sources[0x15]	5674	1			T1	1		T5	2		T15	1
valid_sources[0x16]	5878	1			T5	2		T15	11		T7	1
valid_sources[0x17]	5995	1			T5	2		T15	3		T19	4
valid_sources[0x18]	5467	1			T5	4		T15	17		T19	8
valid_sources[0x19]	5941	1			T3	9		T5	1		T19	5
valid_sources[0x1a]	7173	1			T5	3		T15	6		T8	3
valid_sources[0x1b]	8283	1			T15	11		T7	2		T19	7
valid_sources[0x1c]	5922	1			T5	5		T15	6		T7	8
valid_sources[0x1d]	5965	1			T3	15		T5	2		T15	12
valid_sources[0x1e]	9306	1			T5	7		T15	9		T19	10
valid_sources[0x1f]	5755	1			T5	3		T15	22		T8	7
valid_sources[0x20]	23876	1			T3	9		T5	1		T15	7
valid_sources[0x21]	5716	1			T5	1		T15	1		T19	8
valid_sources[0x22]	6183	1			T5	3		T15	3		T19	16
valid_sources[0x23]	6055	1			T1	1		T3	8		T5	3
valid_sources[0x24]	6064	1			T3	3		T5	4		T15	7
valid_sources[0x25]	5820	1			T1	2		T15	4		T7	11
valid_sources[0x26]	5729	1			T19	24		T27	5		T26	11
valid_sources[0x27]	5610	1			T2	1		T15	6		T19	3
valid_sources[0x28]	9977	1			T5	1		T15	5		T26	12
valid_sources[0x29]	6987	1			T5	5		T15	12		T19	6
valid_sources[0x2a]	6770	1			T3	25		T5	1		T15	3
valid_sources[0x2b]	7306	1			T5	3		T26	11		T25	6
valid_sources[0x2c]	6011	1			T5	3		T15	1		T19	10
valid_sources[0x2d]	8427	1			T5	5		T15	5		T8	2
valid_sources[0x2e]	5769	1			T3	4		T5	1		T7	1
valid_sources[0x2f]	6004	1			T3	22		T15	7		T19	1
valid_sources[0x30]	5819	1			T1	1		T5	1		T15	10
valid_sources[0x31]	6929	1			T3	6		T15	4		T27	4
valid_sources[0x32]	6205	1			T1	2		T5	1		T15	7
valid_sources[0x33]	6966	1			T3	6		T5	2		T15	13
valid_sources[0x34]	5792	1			T1	1		T5	1		T15	2
valid_sources[0x35]	6328	1			T5	1		T15	2		T8	3
valid_sources[0x36]	5974	1			T19	12		T26	17		T25	11
valid_sources[0x37]	5871	1			T3	14		T5	2		T15	8
valid_sources[0x38]	9809	1			T3	7		T5	7		T15	1
valid_sources[0x39]	5912	1			T15	4		T19	7		T26	15
valid_sources[0x3a]	5888	1			T5	2		T15	7		T19	8
valid_sources[0x3b]	5852	1			T5	2		T8	1		T19	6
valid_sources[0x3c]	7457	1			T1	1		T5	2		T15	2
valid_sources[0x3d]	5962	1			T5	1		T15	3		T8	1
valid_sources[0x3e]	6051	1			T3	4		T5	2		T15	3
valid_sources[0x3f]	7277	1			T3	3		T5	1		T15	9
valid_sources[0x40]	5835	1			T3	3		T5	2		T15	3
valid_sources[0x41]	6014	1			T5	2		T7	4		T19	8
valid_sources[0x42]	6054	1			T15	15		T19	11		T27	2
valid_sources[0x43]	6481	1			T3	3		T5	3		T15	7
valid_sources[0x44]	8207	1			T1	3		T15	5		T19	9
valid_sources[0x45]	5779	1			T5	1		T15	10		T19	9
valid_sources[0x46]	5957	1			T3	12		T5	1		T15	10
valid_sources[0x47]	5976	1			T5	3		T15	1		T19	7
valid_sources[0x48]	7032	1			T1	1		T5	2		T15	13
valid_sources[0x49]	15482	1			T15	3		T7	7		T19	3
valid_sources[0x4a]	6169	1			T3	21		T5	2		T15	10
valid_sources[0x4b]	6339	1			T5	2		T15	14		T19	10
valid_sources[0x4c]	7383	1			T15	9		T7	3		T19	2
valid_sources[0x4d]	6178	1			T15	12		T19	3		T26	23
valid_sources[0x4e]	6535	1			T5	2		T19	5		T26	12
valid_sources[0x4f]	5660	1			T3	10		T5	1		T15	21
valid_sources[0x50]	5886	1			T3	9		T5	2		T15	1
valid_sources[0x51]	6111	1			T15	9		T19	12		T26	14
valid_sources[0x52]	5777	1			T1	2		T15	7		T19	26
valid_sources[0x53]	5906	1			T3	3		T5	1		T15	4
valid_sources[0x54]	6667	1			T1	1		T3	14		T5	2
valid_sources[0x55]	5878	1			T15	5		T19	28		T26	10
valid_sources[0x56]	5683	1			T5	2		T15	10		T8	1
valid_sources[0x57]	5968	1			T3	2		T5	3		T15	3
valid_sources[0x58]	5701	1			T5	1		T15	1		T19	24
valid_sources[0x59]	5713	1			T5	3		T15	6		T8	2
valid_sources[0x5a]	6822	1			T15	2		T19	9		T26	10
valid_sources[0x5b]	7253	1			T3	13		T5	1		T15	10
valid_sources[0x5c]	5868	1			T3	33		T5	5		T15	1
valid_sources[0x5d]	6528	1			T5	2		T27	2		T26	10
valid_sources[0x5e]	10005	1			T3	34		T5	3		T15	2
valid_sources[0x5f]	7779	1			T15	6		T19	6		T26	8
valid_sources[0x60]	5995	1			T5	1		T15	1		T8	1
valid_sources[0x61]	5574	1			T3	13		T5	2		T15	1
valid_sources[0x62]	6191	1			T3	9		T5	3		T15	4
valid_sources[0x63]	7149	1			T15	2		T8	7		T27	4
valid_sources[0x64]	7032	1			T1	1		T3	2		T5	1
valid_sources[0x65]	5420	1			T5	1		T15	1		T19	10
valid_sources[0x66]	16417	1			T15	13		T19	8		T27	2
valid_sources[0x67]	6770	1			T1	1		T15	4		T19	4
valid_sources[0x68]	5754	1			T15	14		T19	8		T26	6
valid_sources[0x69]	5599	1			T5	1		T15	5		T19	10
valid_sources[0x6a]	5604	1			T5	3		T27	1		T26	8
valid_sources[0x6b]	10530	1			T5	1		T15	6		T19	10
valid_sources[0x6c]	6083	1			T5	1		T15	9		T26	17
valid_sources[0x6d]	7352	1			T5	2		T15	4		T19	5
valid_sources[0x6e]	6201	1			T15	5		T8	2		T19	9
valid_sources[0x6f]	12700	1			T5	4		T15	14		T8	2
valid_sources[0x70]	6655	1			T5	5		T15	3		T8	3
valid_sources[0x71]	6010	1			T5	2		T15	6		T27	5
valid_sources[0x72]	5967	1			T3	9		T5	1		T15	1
valid_sources[0x73]	5647	1			T1	1		T3	6		T15	1
valid_sources[0x74]	6071	1			T1	1		T3	11		T15	5
valid_sources[0x75]	5719	1			T1	1		T5	2		T15	4
valid_sources[0x76]	5923	1			T2	2		T3	3		T5	2
valid_sources[0x77]	5948	1			T3	8		T5	1		T15	1
valid_sources[0x78]	6049	1			T5	1		T19	4		T27	7
valid_sources[0x79]	6190	1			T3	5		T5	5		T15	6
valid_sources[0x7a]	6284	1			T19	5		T26	8		T25	10
valid_sources[0x7b]	81442	1			T15	1		T7	2		T19	4
valid_sources[0x7c]	5805	1			T1	2		T5	1		T15	4
valid_sources[0x7d]	5747	1			T5	1		T15	1		T8	3
valid_sources[0x7e]	5472	1			T5	3		T15	3		T19	4
valid_sources[0x7f]	5945	1			T1	1		T15	8		T7	3
valid_sources[0x80]	5607	1			T5	5		T15	12		T19	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

767529

1

T3

365

T4

52

T5

107

values[0x0]

all_enables

biggest_size

127449

1

T1

3

T3

44

T4

45

values[0x1]

all_enables

biggest_size

125967

1

T1

2

T3

54

T4

36