Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	64083521	14484	0	0
claim_transition_if_regwen_rd_A	64083521	944	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64083521	14484	0	0
T56	17384	0	0	0
T58	0	5	0	0
T74	227042	1	0	0
T90	42119	0	0	0
T163	0	10	0	0
T164	0	16	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	2	0	0
T168	0	4	0	0
T169	0	4	0	0
T170	0	5	0	0
T171	32739	0	0	0
T172	46740	0	0	0
T173	22597	0	0	0
T174	283715	0	0	0
T175	70836	0	0	0
T176	3525	0	0	0
T177	69730	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64083521	944	0	0
T35	49292	0	0	0
T74	0	1	0	0
T84	1098	0	0	0
T105	159408	3	0	0
T109	0	4	0	0
T133	0	12	0	0
T178	0	7	0	0
T179	0	64	0	0
T180	0	2	0	0
T181	0	27	0	0
T182	0	5	0	0
T183	0	39	0	0
T184	66261	0	0	0
T185	29025	0	0	0
T186	3739	0	0	0
T187	83942	0	0	0
T188	80928	0	0	0
T189	23845	0	0	0
T190	165268	0	0	0