Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	712657	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

898400

1

T1

5

T2

105

T3

94

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1320209	1			T1	3		T2	92		T3	92
values[0x0]	144712	1			T1	3		T2	44		T3	26
values[0x1]	146136	1			T1	5		T2	33		T3	30

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	562326	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1048731

1

T1

7

T2

118

T3

104

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4447	1			T4	4		T27	1		T25	1
valid_sources[0x01]	7987	1			T4	6		T5	1		T40	2
valid_sources[0x02]	4401	1			T2	2		T4	2		T5	3
valid_sources[0x03]	5705	1			T27	5		T26	21		T23	9
valid_sources[0x04]	4648	1			T5	3		T16	10		T25	3
valid_sources[0x05]	4932	1			T2	1		T4	1		T5	1
valid_sources[0x06]	4498	1			T4	2		T25	3		T40	3
valid_sources[0x07]	5681	1			T2	2		T12	9		T27	1
valid_sources[0x08]	4331	1			T4	1		T27	1		T25	1
valid_sources[0x09]	5299	1			T2	2		T27	5		T25	1
valid_sources[0x0a]	8732	1			T4	2		T27	1		T25	1
valid_sources[0x0b]	4423	1			T4	1		T12	37		T27	1
valid_sources[0x0c]	4589	1			T2	2		T4	1		T5	1
valid_sources[0x0d]	4408	1			T4	2		T12	16		T16	15
valid_sources[0x0e]	4372	1			T4	2		T27	1		T25	2
valid_sources[0x0f]	4406	1			T1	2		T4	1		T12	4
valid_sources[0x10]	21676	1			T2	7		T4	1		T27	12
valid_sources[0x11]	14504	1			T1	1		T4	2		T5	2
valid_sources[0x12]	5286	1			T12	2		T16	22		T25	2
valid_sources[0x13]	6011	1			T4	4		T16	3		T27	3
valid_sources[0x14]	8628	1			T5	1		T12	5		T27	1
valid_sources[0x15]	4677	1			T2	1		T27	2		T25	4
valid_sources[0x16]	24405	1			T2	1		T4	2		T27	2
valid_sources[0x17]	6402	1			T4	2		T12	1		T27	6
valid_sources[0x18]	5640	1			T2	1		T4	1		T27	13
valid_sources[0x19]	18239	1			T2	2		T12	5		T16	13
valid_sources[0x1a]	4430	1			T4	2		T25	1		T26	26
valid_sources[0x1b]	4243	1			T2	3		T4	3		T27	5
valid_sources[0x1c]	4331	1			T27	1		T25	1		T26	21
valid_sources[0x1d]	4388	1			T27	2		T25	2		T26	24
valid_sources[0x1e]	4504	1			T2	1		T4	2		T27	3
valid_sources[0x1f]	4375	1			T1	1		T2	1		T12	29
valid_sources[0x20]	3931	1			T4	1		T12	14		T27	1
valid_sources[0x21]	4260	1			T4	1		T16	1		T27	3
valid_sources[0x22]	4437	1			T4	1		T12	3		T26	25
valid_sources[0x23]	6210	1			T2	1		T3	148		T4	1
valid_sources[0x24]	7050	1			T4	2		T5	5		T12	1
valid_sources[0x25]	4401	1			T27	1		T25	3		T40	1
valid_sources[0x26]	4196	1			T4	3		T27	1		T25	1
valid_sources[0x27]	4215	1			T4	2		T27	14		T25	2
valid_sources[0x28]	4442	1			T2	1		T16	35		T25	1
valid_sources[0x29]	4683	1			T4	2		T12	4		T40	1
valid_sources[0x2a]	6035	1			T27	6		T25	2		T26	21
valid_sources[0x2b]	6441	1			T12	7		T27	2		T25	1
valid_sources[0x2c]	4988	1			T4	5		T7	71		T12	26
valid_sources[0x2d]	4465	1			T4	3		T12	4		T27	7
valid_sources[0x2e]	5962	1			T2	2		T25	1		T26	20
valid_sources[0x2f]	4474	1			T4	1		T27	2		T25	2
valid_sources[0x30]	4465	1			T4	3		T16	28		T25	1
valid_sources[0x31]	4426	1			T4	1		T27	7		T25	1
valid_sources[0x32]	6794	1			T25	1		T26	23		T23	11
valid_sources[0x33]	21255	1			T4	1		T12	3		T27	2
valid_sources[0x34]	7593	1			T4	1		T5	1		T16	22
valid_sources[0x35]	4375	1			T27	3		T25	2		T40	2
valid_sources[0x36]	5605	1			T27	3		T25	3		T26	27
valid_sources[0x37]	4018	1			T2	3		T25	1		T26	23
valid_sources[0x38]	9816	1			T2	1		T5	1		T27	1
valid_sources[0x39]	4272	1			T4	1		T25	2		T22	17
valid_sources[0x3a]	6288	1			T27	2		T25	1		T40	1
valid_sources[0x3b]	5335	1			T4	2		T12	2		T16	32
valid_sources[0x3c]	5122	1			T4	1		T16	17		T25	3
valid_sources[0x3d]	4338	1			T12	2		T27	1		T40	3
valid_sources[0x3e]	4296	1			T2	1		T12	11		T16	21
valid_sources[0x3f]	8412	1			T2	1		T4	2		T12	5
valid_sources[0x40]	4495	1			T2	1		T4	3		T5	4
valid_sources[0x41]	4379	1			T2	9		T4	1		T12	2
valid_sources[0x42]	6261	1			T2	1		T4	1		T12	18
valid_sources[0x43]	4368	1			T5	5		T12	19		T25	2
valid_sources[0x44]	4572	1			T25	2		T26	27		T23	5
valid_sources[0x45]	8010	1			T4	1		T12	21		T16	3
valid_sources[0x46]	5565	1			T4	1		T16	17		T27	1
valid_sources[0x47]	4540	1			T2	2		T12	13		T27	4
valid_sources[0x48]	4467	1			T4	3		T12	2		T16	4
valid_sources[0x49]	6007	1			T4	1		T25	2		T26	32
valid_sources[0x4a]	4890	1			T4	1		T12	1		T27	3
valid_sources[0x4b]	4283	1			T4	5		T27	5		T25	1
valid_sources[0x4c]	4217	1			T4	3		T12	17		T27	4
valid_sources[0x4d]	4259	1			T27	5		T25	1		T26	25
valid_sources[0x4e]	4040	1			T1	1		T2	3		T4	3
valid_sources[0x4f]	5973	1			T4	1		T5	1		T12	53
valid_sources[0x50]	4366	1			T4	3		T5	3		T27	4
valid_sources[0x51]	4747	1			T4	1		T31	38		T27	4
valid_sources[0x52]	6404	1			T12	28		T27	3		T25	1
valid_sources[0x53]	8125	1			T2	1		T4	4		T27	5
valid_sources[0x54]	4498	1			T4	1		T12	2		T26	25
valid_sources[0x55]	4907	1			T5	2		T12	16		T25	2
valid_sources[0x56]	18842	1			T4	3		T12	4		T16	62
valid_sources[0x57]	4720	1			T4	1		T25	1		T40	2
valid_sources[0x58]	4428	1			T5	6		T12	14		T27	8
valid_sources[0x59]	4303	1			T12	4		T27	3		T25	1
valid_sources[0x5a]	7200	1			T26	30		T23	9		T18	27
valid_sources[0x5b]	4423	1			T27	3		T26	26		T23	10
valid_sources[0x5c]	4315	1			T4	1		T7	4		T16	22
valid_sources[0x5d]	5145	1			T25	2		T26	23		T23	3
valid_sources[0x5e]	4252	1			T4	1		T27	2		T25	1
valid_sources[0x5f]	4301	1			T4	1		T40	1		T26	23
valid_sources[0x60]	6970	1			T27	1		T25	2		T26	30
valid_sources[0x61]	4440	1			T2	1		T4	1		T5	1
valid_sources[0x62]	4551	1			T2	3		T4	3		T12	5
valid_sources[0x63]	9010	1			T4	2		T12	27		T27	11
valid_sources[0x64]	5505	1			T4	5		T12	6		T25	1
valid_sources[0x65]	20099	1			T4	3		T5	1		T12	1
valid_sources[0x66]	6811	1			T11	3		T25	2		T40	1
valid_sources[0x67]	4674	1			T25	1		T26	35		T23	5
valid_sources[0x68]	4218	1			T12	6		T16	18		T27	3
valid_sources[0x69]	6666	1			T1	1		T4	1		T16	5
valid_sources[0x6a]	4458	1			T4	1		T12	5		T27	11
valid_sources[0x6b]	7664	1			T27	2		T25	1		T26	25
valid_sources[0x6c]	5009	1			T2	1		T4	4		T12	25
valid_sources[0x6d]	5665	1			T25	1		T26	28		T23	5
valid_sources[0x6e]	4645	1			T4	1		T27	1		T25	3
valid_sources[0x6f]	4605	1			T12	12		T27	17		T40	3
valid_sources[0x70]	4124	1			T2	1		T4	1		T12	2
valid_sources[0x71]	4455	1			T4	3		T25	2		T26	19
valid_sources[0x72]	5369	1			T2	4		T4	3		T16	5
valid_sources[0x73]	6106	1			T12	11		T27	2		T25	4
valid_sources[0x74]	4251	1			T4	1		T12	6		T25	1
valid_sources[0x75]	5859	1			T12	5		T27	3		T40	3
valid_sources[0x76]	4382	1			T4	1		T12	19		T27	4
valid_sources[0x77]	4345	1			T2	1		T4	1		T27	1
valid_sources[0x78]	4246	1			T5	1		T12	5		T40	1
valid_sources[0x79]	4000	1			T2	4		T16	3		T40	3
valid_sources[0x7a]	7192	1			T27	7		T25	2		T40	1
valid_sources[0x7b]	25375	1			T4	2		T27	3		T215	1
valid_sources[0x7c]	4562	1			T4	1		T12	3		T26	34
valid_sources[0x7d]	4374	1			T4	2		T16	20		T27	4
valid_sources[0x7e]	4617	1			T12	3		T16	142		T26	22
valid_sources[0x7f]	4402	1			T16	25		T27	1		T25	1
valid_sources[0x80]	4253	1			T2	3		T4	1		T25	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

648188

1

T2

44

T3

46

T11

1

values[0x0]

all_enables

biggest_size

125303

1

T1

2

T2

35

T3

19

values[0x1]

all_enables

biggest_size

124909

1

T1

3

T2

26

T3

29