Unified Coverage Report :: Module :: tlul_rsp_intg_chk

Module : tlul_rsp_intg_chk

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	100.00	40.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tap_tlul_host.u_rsp_chk	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_tap_tlul_host.u_rsp_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.77	100.00	100.00	15.09			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.78	95.45	91.67			100.00	100.00	u_tap_tlul_host

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_chk	15.09			15.09

Line Coverage for Module : tlul_rsp_intg_chk

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	23	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	50	1	1	100.00

22                        tl_d2h_rsp_intg_t rsp;
23         1/1            assign rsp = extract_d2h_rsp_intg(tl_i);
           Tests:       T1 T2 T3 
24                      
25                        prim_secded_inv_64_57_dec u_chk (
26                          .data_i({tl_i.d_user.rsp_intg, D2HRspMaxWidth'(rsp)}),
27                          .data_o(),
28                          .syndrome_o(),
29                          .err_o(rsp_err)
30                        );
31                      
32                        logic rsp_data_err;
33                        if (EnableRspDataIntgCheck) begin : gen_rsp_data_intg_check
34                          tlul_data_integ_dec u_tlul_data_integ_dec (
35                            .data_intg_i({tl_i.d_user.data_intg, DataMaxWidth'(tl_i.d_data)}),
36                            .data_err_o(rsp_data_err)
37                          );
38                        end else begin : gen_no_rsp_data_intg_check
39                          assign rsp_data_err = 1'b0;
40                        end
41                      
42                        // error is not permanently latched as rsp_intg_chk is typically
43                        // used near the host.
44                        // if the error is permanent, it would imply the host could forever
45                        // receive bus errors and lose all ability to debug.
46                        // It should be up to the host to determine the permanence of this error.
47         1/1            assign err_o = tl_i.d_valid & (|rsp_err | rsp_data_err);
           Tests:       T1 T2 T3 
48                      
49                        logic unused_tl;
50         1/1            assign unused_tl = |tl_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : tlul_rsp_intg_chk

	Total	Covered	Percent
Conditions	5	2	40.00
Logical	5	2	40.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION (tl_i.d_valid & (((|rsp_err)) | rsp_data_err))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Not Covered

 LINE       47
 SUB-EXPRESSION (((|rsp_err)) | rsp_data_err)
                 ------1-----   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Not Covered

---

Assert Coverage for Module : tlul_rsp_intg_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	812	812	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	812	812	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_tap_tlul_host.u_rsp_chk

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	23	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	50	1	1	100.00

22                        tl_d2h_rsp_intg_t rsp;
23         1/1            assign rsp = extract_d2h_rsp_intg(tl_i);
           Tests:       T1 T2 T3 
24                      
25                        prim_secded_inv_64_57_dec u_chk (
26                          .data_i({tl_i.d_user.rsp_intg, D2HRspMaxWidth'(rsp)}),
27                          .data_o(),
28                          .syndrome_o(),
29                          .err_o(rsp_err)
30                        );
31                      
32                        logic rsp_data_err;
33                        if (EnableRspDataIntgCheck) begin : gen_rsp_data_intg_check
34                          tlul_data_integ_dec u_tlul_data_integ_dec (
35                            .data_intg_i({tl_i.d_user.data_intg, DataMaxWidth'(tl_i.d_data)}),
36                            .data_err_o(rsp_data_err)
37                          );
38                        end else begin : gen_no_rsp_data_intg_check
39                          assign rsp_data_err = 1'b0;
40                        end
41                      
42                        // error is not permanently latched as rsp_intg_chk is typically
43                        // used near the host.
44                        // if the error is permanent, it would imply the host could forever
45                        // receive bus errors and lose all ability to debug.
46                        // It should be up to the host to determine the permanence of this error.
47         1/1            assign err_o = tl_i.d_valid & (|rsp_err | rsp_data_err);
           Tests:       T1 T2 T3 
48                      
49                        logic unused_tl;
50         1/1            assign unused_tl = |tl_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_tap_tlul_host.u_rsp_chk

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION (tl_i.d_valid & (((|rsp_err)) | rsp_data_err))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T5,T6,T7
1	1	Excluded		VC_COV_UNR

 LINE       47
 SUB-EXPRESSION (((|rsp_err)) | rsp_data_err)
                 ------1-----   ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Excluded		VC_COV_UNR

---

Assert Coverage for Instance : tb.dut.u_tap_tlul_host.u_rsp_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	812	812	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	812	812	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0